Micron Technology Incorporated

Round Rock Research, LLC

Microsoft Technology Licensing, LLC

Micron Semiconductor, Inc.

Timothy B Cowles

James S Rehmeyer

Jonathan Scott Parry

George B Raad

Jeffrey P Wright

Brendan N Protzman

Nathaniel J Meier

Jiyun Li

Todd A Merritt

Aron T Lunde

Steve Casper

Troy A Manning

Dong Pan

Christian N Mohr

Brent Keeth

Paul A LaBerge

Greg A Blodgett

Brian M Shirley

Joe M Jeddeloh

Chris G Martin

Hua Zheng

Victor Wong

Steven G Renfro

Steven M Bodily

Jim Rehmeyer

Dean D Gans

Michael Amiel Shore

Randall J Rooney

Jeffrey Edward Koelling

Beau D Barry

Adam J Grenzebach

Jeffery P Wright

R Jacob Baker

Daniel B Penney

Aaron M Schoenfeld

Wen Qian Li

Mark R Thomann

Jason M Brown

Daniel R Loughmiller

Dennis G Montierth

William F Jones

Danial S Dean

James S Cullum

Matthew D Jenkinson

Vikram K Bollu

Brian J Ladner

Frank Alejano

Paul M Prew

Kevin G Duesman

Charles L Ingalls

John Frederic Schreck

Patrick J Mullarkey

Rich Fogal

Terry M Grunzke

Tracy V Reynolds

Todd A Merrit

Provided herein are memory devices, systems including memory devices, and methods of operating memory devices in which multiple counters are provided to permit memory refresh commands greater freedom in targeting subsets of the memory device for data refresh operations. In one embodiment, a memory device is provided, comprising a plurality of memory banks, and circuitry configured to (i) store a plurality of values, each of the plurality of values corresponding to one of the plurality of memory banks; (ii) refresh first data stored in a first one of the plurality of memory banks; and (iii) update a first one of the plurality of values corresponding to the first one of the plurality of memory banks based at least in part on refreshing the first data.

Methods for independent memory bank maintenance and memory devices and systems employing the same

Memory devices and methods of operating memory devices in which refresh management operations can be scheduled on an as-needed basis for those memory portions where activity (e.g., activations in excess of a predetermined threshold) warrants a refresh management operation are disclosed. In one embodiment, an apparatus comprises a memory including a memory location, and circuitry configured to determine a count corresponding to a number of activations at the memory location, to schedule a refresh management operation for the memory location in response to the count exceeding a first predetermined threshold, and to decrease the count by an amount corresponding to the first predetermined threshold in response to executing the scheduled refresh management operation. The circuitry may be further configured to disallow, in response to determining that the count has reached a maximum permitted value, further activations at the memory location until after the count has been decreased.

Methods for row hammer mitigation and memory devices and systems employing the same

The address of victim rows may be determined based on rows that are accessed in a memory. The victim addresses may be stored and associated with a count for every time a victim row is 'victimized.' When the count for a victim row reaches a threshold, the victim row may be refreshed to preserve data stored in the row. After the victim row has been refreshed, the count may be reset. When a victim row is accessed, the count may also be reset. The counts may be adjusted for closer victim rows (e.g., +/−1) at a faster rate than counts for more distant victim rows (e.g., +/−2). This may cause closer victim rows to be refreshed at a higher rate than more distant victim rows.

Apparatuses and methods for tracking victim rows

An apparatus may include a refresh control circuit with multiple timing circuits. The timing circuits may be used to control steal rates, e.g., the rate of refresh time slots dedicated to healing victim word lines of row hammers. The timing circuits may be controlled to allow independent adjustment of the steal rates for different victim word lines. Thus, different victim word lines may be refreshed at different rates and the different rates may be independent of one another.

Apparatuses and methods for controlling steal rates

Memory devices, systems including memory devices, and methods of operating memory devices and systems are provided, in which at least a subset of a non-volatile memory array is configured to behave as read-only memory by not implementing erase or write commands. In one embodiment of the present technology, a memory device is provided, comprising a non-volatile memory array, and circuitry configured to store one or more addresses of the non-volatile memory array, to compare an address of a received command to the one or more addresses, and at least in part based on the comparison, determine not to implement the received command. The circuitry can be further configured to return an error message after determining not to implement the received command.

Non-volatile memory devices and systems with read-only memory features and methods for operating the same

Memory devices, systems including memory devices, and methods of operating memory devices and systems are provided, in which at least a subset of a non-volatile memory array is configured to behave as a volatile memory by erasing or degrading data in the event of a changed power condition such as a power-loss event, a power-off event, or a power-on event. In one embodiment of the present technology, a memory device is provided, comprising a non-volatile memory array, and circuitry configured to store one or more addresses of the non-volatile memory array, to detect a changed power condition of the memory device, and to erase or degrade data at the one or more addresses in response to detecting the changed power condition.

Non-volatile memory devices and systems with volatile memory features and methods for operating the same

Memory devices, system, and methods for operating the same are provided. The memory device can comprise a non-volatile memory array and control circuitry. The control circuitry can be configured to store a value corresponding to a number of activate commands received at the memory device, update the value in response to receiving an activate command received from a host device, and trigger, in response to the value exceeding a predetermined threshold, a remedial action performed by the memory device. The control circuitry can be further configured to store a second value corresponding to a number of refresh operations performed by the memory device, update the second value in response to performing a refresh operation, and trigger, in response to the value exceeding a second predetermined threshold, a second remedial action performed by the memory device.

Methods for detecting and mitigating memory media degradation and memory devices employing the same

The present disclosure includes apparatuses and methods related to data movement operations in non-volatile memory. An example apparatus can comprise an array of non-volatile memory cells including a plurality of sections each with a plurality of rows and a controller configured to move data stored in a first portion of the array from a first row of a first section to a second row of the first section and move data stored in a second portion of the array from a second section to the first to create an open row in the second section in response to data from a particular number of portions of memory cells in the first section being moved within the first section.

Data movement operations in non-volatile memory

The address of victim rows may be determined based on rows that are accessed in a memory. The victim addresses may be stored and associated with a count for every time a victim row is 'victimized.' When the count for a victim row reaches a threshold, the victim row may be refreshed to preserve data stored in the row. After the victim row has been refreshed, the count may be reset. When a victim row is accessed, the count may also be reset. The counts may be adjusted for closer victim rows (e.g., +/&#x2212;1) at a faster rate than counts for more distant victim rows (e.g., +/&#x2212;2). This may cause closer victim rows to be refreshed at a higher rate than more distant victim rows.

A volatile memory device is configured to self-document by identifying its own bad or at-risk excludable memory locations in a nonvolatile identification embedded in itself, without using additional board real estate. The identification of bad or at-risk memory is readable by firmware outside the device. The device includes volatile memory cells that have respective failure susceptibility values, some of which indicate bad or at-risk memory cells. The memory device also includes read logic and write logic, and may include refresh logic. The identification may be embedded in the device by blowing fuses in an adaptation of self-repair activity, or by writing identification data into a serial presence detect logic, for example. The configured memory device may efficiently, persistently, and reliably provide detailed memory test results regarding itself, thereby allowing customers to accept and safely use memory that would otherwise have been discarded to prevent software crashes.

At-risk memory location identification and management

Growing community of inventors

Boise, ID, United States of America

Timothy B Cowles