Xcerra Corporation

Ltx Corporation

Timothy Alton

William A Fritzsche

Russell Elliott Poffenberger

Michael Gordon Davis

Jeffery D Currin

Mark E Deome

R Warren Necoechea

James Michael Jula

Michael E Amy

Warren Necoechea

Henk Zantman

A segmented subsystem, for use within an automated test platform, includes a first subsystem segment including a first data sequencer configured to coordinate the execution of one or more instructions within the first subsystem segment. A second subsystem segment includes a second data sequencer configured to coordinate the execution of one or more instructions within the second subsystem segment.

Automated test platform utilizing segmented data sequencers to provide time controlled test sequences to device under test

A scalable test platform includes a PCIe-based event fabric. One or more CPU subsystems are coupled to the PCIe-based event fabric and configured to execute an automated test process. One or more instrument subsystems are coupled to the PCIe-based event fabric and configured to interface one or more devices under test.

Scalable test platform in a PCI express environment with direct memory access

A scalable test platform includes a PCIe-based event fabric. One or more instrument subsystems are coupled to the PCIe-based event fabric and configured to interface one or more devices under test and generate captured test data. One or more digital signal processing subsystems are coupled to the PCIe-based event fabric and configured to process the captured test data.

A method, computer program product, and computing system for, upon the occurrence of a computer-related event, comparing code utilized by one or more subsystems included within a scalable test platform to code available from a remote location. If the code available from the remote location is newer than the code utilized by one or more subsystems, the code available from the remote location is obtained, thus defining newer code. The code utilized by one or more subsystems is updated with the newer code.

Scalable test platform

A method is described for facilitating use of a first pattern utilizing XOR data formatting in an electronic tester. The method includes dividing the first pattern into at least a first group and a second group, the tester to successively execute the first group and the second group. The method further includes assuming an entry state for each group is one of two binary conditions and inverting programmed commands for the second group if an ending state of the first group is not equal to the assumed entry state.

Pattern correction circuit

A method and apparatus for generating timing markers in an automatic electrical test system. Timing parameters are synchronized by an external period start signal corresponding to a centrally generated external period and an internal period start signal generated locally for each input/output pin. The timing parameters comprise T1 counter and vernier values, T2 counter and vernier values, and period-minus-T1 counter and period vernier values.

Growing community of inventors

Gilroy, CA, United States of America

Timothy Alton