Unisys Corporation

Timothy Allen Barr

James Rhodes

Robert David Conklin

A system for testing IC chips selectively with stored or internally generated bit streams is comprised of a memory which stores instructions of a first class that expressly recite a first bit stream, and stores instructions of a second class that specify operations which generate a second bit stream. A first pattern generator is coupled to the memory, which sequentially reads the instructions of the first and second classes. The first pattern generator includes a time-shared control circuit which sends the first bit stream to a test port on the chips that are tested in response to the first class instructions that are read. In addition, a second pattern generator is coupled to the first pattern generator. This second pattern generator receives the second class instructions that are read; and in response, it sequentially generates portions of the second bit stream by performing the operations which the second class instructions specify. One portion of the second bit stream is sent to the test port on the chips that are tested, while the second pattern generator generates another portion of the second bit stream.

System for testing IC chips selectively with stored or internally generated bit streams

A system for testing integrated circuit chips is comprised of a pattern generator that is coupled to a memory which stores variable length instructions that specify sets of bit streams for testing the chips. Each variable length instruction includes a code which indicates the number of bit streams in the set. Each bit stream in the set consists of a selectable number of bits which start on a word boundary and vary in increments of one bit. If the code indicates that the number of bit streams in a set is only one, then that one bit stream is stored in consecutive words of the memory. If the code indicates the number bit streams in a set is more than one, then those multiple bit streams are stored in an interleaved fashion in consecutive words in the memory. A respective series of unused bits starts immediately after each bit stream and ends on a word boundary. Each series of unused bits causes the next bit stream to start on a word boundary; and, that simplifies the circuitry which the pattern generator uses to address the bit streams.

Program storage device containing instructions that are spaced apart by unused bits that end on word boundaries and which generate chip testing bit streams of any length

A system for testing integrated circuit chips includes a signal generator which generates a clock signal; and a sequential control circuit having a first input which receives the clock signal, a second input for receiving commands, and multiple outputs. A command source sends programmable sequences of the commands to the second input of the control circuit; and in response, the control circuit passes the clock signal from the first input to only certain outputs which the commands select. All of the outputs of the control circuit are coupled through respective clock transmitters to different chips which are to be tested; and so in response to the programmable commands, the clock signal is sent sequentially to the chips that are to be tested, in selectable subsets. By such sequencing, the total power dissipation of the chips that are tested can be regulated when the chips are of a type that dissipate a large amount of power when they receive the clock signal, but dissipate substantially less power when they do not receive the clock signal.

Electronic system for testing a set of multiple chips concurrently or sequentially in selectable subsets under program control to limit chip power dissipation

A system for testing integrated circuit chips is comprised of a selectable number of pattern generators, each of which is coupled via a separate bus to a selectable number of chip driver circuits. Each pattern generator also is coupled to a respective memory, which stores different bit streams that are readable one word at a time. In operation, each pattern generator selectively reads the bit streams, word by word, from its respective memory; and its sends the words that are read to all of the chip driver circuits which are coupled to its separate bus, simultaneously. While that is occurring, each chip driver converts the words which it is sent into bit serial test signals which test multiple integrated circuit chips in parallel. Since all of the pattern generators operate in parallel, and since each pattern generator sends bit streams to all of the chip driver circuits that are coupled to its bus simultaneously, a high speed of operation is attained.

Electronic system for testing chips having a selectable number of pattern generators that concurrently broadcast different bit streams to selectable sets of chip driver circuits

Growing community of inventors

Chandler, AZ, United States of America

Timothy Allen Barr