Texas Instruments Corporation

Timothy Alan Rost

Satyavolu Srinivas Papa Rao

Edmund David Burke

Vikas I Gupta

Alwin J Tsao

David B Spratt

Gregory Charles Baldwin

E Ajith Amerasekera

Kenneth C Harvey

Deems R Hollingsworth

Rose Alyssa Keagy

Vijay Kumar Reddy

William R Hunter

Cynthia Ann Torres

Bradley Scott Young

Senthil Kumar Sundaramoorthy

Victor James Nuss

An electrostatic discharge (ESD)-triggered protection apparatus includes a first circuit and a second circuit. The first circuit includes an ESD trigger circuit to sense an ESD pulse and to generate a switching pulse responsive to the ESD pulse; a first ESD discharge device communicatively coupled to the ESD trigger circuit and responsive to the switching pulse to transfer a current generated by the ESD pulse to the ground rail; a control circuit that generates a control signal in response to the switching pulse. The second circuit includes at least one trigger cell buffer that is configured to receive the control signal and to control a second ESD discharge device such that the current generated by the ESD pulse is transferred to the ground rail.

Electrostatic discharge protection apparatus

An on-chip decoupling capacitor () and method of fabrication. The decoupling capacitor () is integrated at the top metal interconnect level () and includes surface protection cladding () for the copper metal () of the top metal interconnect.

Capacitor integration at top-metal level with a protective cladding for copper surface protection

The present invention facilitates semiconductor device fabrication and performance by providing a semiconductor device that can improve channel mobility for both N type and P type transistor devices. The semiconductor device of the present invention is fabricated on a semiconductor substratethat has a first and second crystallographic orientation axes (e.g., &#x3c;110&#x3e;, &#x3c;100&#x3e;)andSource to drain channel regions for P type devices are formedand aligned along the first crystallographic orientation axis. Source to drain channel regions for N type devices are formedrotated from the channel regions of the P type devices by an offset angle so that the source to drain channel regions for the N type devices are aligned with the second crystallographic orientation axis. Subsequently, a uniaxial or biaxial tensile stressis applied to the source to drain channel regions of the N type devices and a uniaxial or biaxial compressive stressis applied to the source to drain channel regions of the P type devices.

Transistor design and layout for performance improvement with strain

The present invention facilitates semiconductor device fabrication and performance by providing a semiconductor device that can improve channel mobility for both N type and P type transistor devices. The semiconductor device of the present invention is fabricated on a semiconductor substratethat has a first and second crystallographic orientation axes (e.g., &#x3c;110&#x3e;, &#x3c;100&#x3e;)and. Source to drain channel regions for P type devices are formedand aligned along the first crystallographic orientation axis. Source to drain channel regions for N type devices are formedrotated from the channel regions of the P type devices by an offset angle so that the source to drain channel regions for the N type devices are aligned with the second crystallographic orientation axis. Subsequently, a uniaxial or biaxial tensile stressis applied to the source to drain channel regions of the N type devices and a uniaxial or biaxial compressive stressis applied to the source to drain channel regions of the P type devices.

An on-chip decoupling capacitor () and method of fabrication. The decoupling capacitor () is integrated at the top metal interconnect level () and may be implemented with only one additional masking layer. The decoupling capacitor () is formed on a copper interconnect line (). An aluminum cap layer () provides electrical connection to the top electrode () of the decoupling capacitor ().

One mask high density capacitor for integrated circuits

Disclosed are apparatus and method for limiting mobile charge () ingress within a silicon-on-insulator (SOI) substrate (). A mask () is applied to the substrate to form an aperture () over a desired portion of the substrate near its outer edge. A buffer material (), selected to impede mobile charge ingress, is implanted () through the aperture into the insulator layer () of the substrate to form a buffer structure ().

Versatile system for limiting mobile charge ingress in SOI semiconductor structures

An on-chip decoupling capacitor () and method of fabrication. The decoupling capacitor () is integrated at the top metal interconnect level () and includes surface protection layer () for the copper metal () of the top metal interconnect.

Capacitor integration at top-metal level with a protection layer for the copper surface

An embodiment of the invention is a capacitor comprising a bottom electrodecoupled to a first interconnectof the top metal levela capacitor dielectricsidewallsand a top electrodecoupled to a second interconnectof the top metal levelAnother embodiment of the invention is a method of manufacturing a capacitor using a first maskto form a material stack that includes a bottom electrodecoupled to a first interconnectof the top metal levela capacitor dielectricand a partial top electrodeThe method further includes using a second maskto form a complete top electrode coupled to a second interconnectof the top metal level

Dual mask capacitor for integrated circuits

An embodiment of the invention is a capacitor comprising a bottom electrodecoupled to a first interconnectof the top metal level, a capacitor dielectric, sidewalls, and a top electrodecoupled to a second interconnectof the top metal level. Another embodiment of the invention is a method of manufacturing a capacitor using a first maskto form a material stack that includes a bottom electrodescoupled to a first interconnectof the top metal level, a capacitor dielectric, and a partial top electrode. The method further includes using a second maskto form a complete top electrode coupled to a second interconnectof the top metal level

A method of testing integrated circuits for the effect of NBTI degradation. A static DC stress voltage is applied to the voltage supply input of the circuit. This circuit is held at this voltage for a given stress period. The application of the DC voltage is equivalent to applying a negative gate bias, and isolates the effects of NBTI degradation from CHC (channel hot carrier) degradation or other degradation that occurs when the circuit has a clocked input.

Method for measuring NBTI degradation effects on integrated circuits

Disclosed are apparatus and method for limiting mobile charge ( ) ingress within a silicon-on-insulator (SOI) substrate ( ). A mask ( ) is applied to the substrate to form an aperture ( ) over a desired portion of the substrate near its outer edge. A buffer material ( ), selected to impede mobile charge ingress, is implanted ( ) through the aperture into the insulator layer ( ) of the substrate to form a buffer structure ( ).

In one embodiment, an integrated circuit includes a heat generating structure within a dielectric region and one or more substantially horizontally arranged heat dissipation layers within the dielectric region. Each heat dissipation layer includes electrically inactive thermally conductive structures, at least two such structures in at least one such layer being substantially horizontally connected and thermally coupled to one another within the layer. The electrically inactive thermally conductive structures cooperate to facilitate dissipation of heat from the heat generating structure. In another embodiment, an integrated circuit includes one or more heat generating structures within a dielectric region and electrically inactive thermal posts formed at least partially within the dielectric region. At least one such post is substantially horizontally connected and thermally coupled to another such post. The electrically inactive thermal posts cooperate to facilitate dissipation of heat from the one or more heat generating structures.

INTEGRATED CIRCUIT PROVIDING THERMALLY CONDUCTIVE STRUCTURES SUBSTANTIALLY HORIZONTALLY COUPLED TO ONE ANOTHER WITHIN ONE OR MORE HEAT DISSIPATION LAYERS TO DISSIPATE HEAT FROM A HEAT GENERATING STRUCTURE

A method of fabricating a semiconductor device wherein there is provided a semiconductor substrate, preferably of silicon, having a gate insulator thereover, preferably of silicon dioxide, forming a junction, preferably a silicon/silicon dioxide interface, and a gate electrode, preferably of doped polysilicon, over the partially fabricated device. Deuterium is implanted into the structure and the deuterium is caused to diffuse through the device. The device fabrication is then completed.

Method for improving performance and reliability of MOS technologies and data retention characteristics of flash memory cells

A method of fabricating a semiconductor device wherein there is provided a semiconductor substrate, preferably of silicon, having a gate insulator thereover, preferably of silicon dioxide, forming a junction, preferably a silicon/silicon dioxide interface, and a gate electrode, preferably of doped polysilicon, over the partially fabricated device. Deuterium is implanted into the structure and the deuterium is caused to diffuse through the deivce. The device fabrication is then completed.

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Plano, TX, United States of America

Timothy Alan Rost