Koninklijke Philips Corporation N.v.

Nxp B.v.

Synopsys, Inc.

Facebook Technologies, LLC

Philips Electronics North America Corporation

Sonics, Incorporated

Philips Semiconductors Inc.

Timothy A Pontius

David R Evoy

Gregory Ehmann

Mark Johnson

Drew Eric Wingard

Mark Bapst

Chien-Chun Chou

D C Sessions

Robert Nolan Payne

Robert L Payne

Jeremy Chan

Kevin L Daberkow

Harutyun Aslanyan

Hervé Jacques Alexanian

Jens Roever

Liewei Bao

Robert J Caesar, Jr

Arjan Bink

Ivan Svestka

George Ellis Spatz

Flow logic supports concurrency of multiple threads and/or tag IDs to be concurrently communicated across the interconnect while allowing the one or more target IP cores to be able to reorder incoming request transactions from the initiator IP core in a manner that is optimal for that target IP core while relieving that target IP core from having to maintain the sequential issue order of transaction responses to the incoming request transactions in the thread or tags when processed by the target IP core. The flow logic cooperates with the reorder storage buffers to control an operation of the reorder storage buffers as well as control issuance of at least the request transactions from the initiator IP core onto the interconnect in order to maintain proper sequential ordering of the transaction responses for the thread or tags when the transaction responses are returned back to the initiator IP core.

Reordering responses in a high performance on-chip network

In certain arrangements and methods, a reset-able counter () produces multiple delay times as required by, for example, a finite state machine. The counter () counts a stored value by a configurable amount. That configurable amount is determined based upon the period of a clock cycle divided by a desired time unit. The value held by the counter does not represent a count of clock cycles, but rather a count of time units. In other aspects, a device generates fixed delays derived from a variable frequency input clock. The device includes a count circuit () and a comparator (). The number of time-units between consecutive clock edges of the input clock is stored, and the count circuit changes a current-count value by a corresponding amount, with the change being responsive to a clock edge of the input clock. The comparator () compares the current-count value to a fixed value that represents a fixed delay time.

Methods and systems related to a configurable delay counter used with variable frequency clocks

A data communication arrangement permits efficient data transfer between a controller module and multiple target modules using a two-phase protocol. The controller module and the target modules can each reside in separate clock domains. Consistent with one example embodiment, a data communication arrangement includes a plurality of target modules, and a first XOR tree arranged to provide a first data integrity-indicating signal and to respond to a respective second data integrity-indicating signal from each of the target modules. A second XOR tree is arranged to provide a first data bus and to respond to a respective second data bus from each of the target modules. Also, a controller module is used to determine availability of data on the first data bus in response to the first data integrity-indicating signal.

Two-phase data-transfer protocol

A method and arrangement of passing data from a source clock domain to a non-synchronous receive clock domain are provided. A first processing circuit, located in the source clock domain, links write-address information with the data, and a clock generator generates a transmit clock signal in the source clock domain synchronous with a source clock. The first processing circuit transmits the clock signal and the data with the linked write-address information to a second processing circuit in the receive clock domain. In the receive clock domain, the second processing circuit writes the data at an address designating a storage element corresponding to the linked write-address information. The second processing circuit clocks the data into the storage element synchronous with the accompanying transmit clock signal responsive to a write enable signal from the source clock domain, and reads the data out of the storage element synchronous with a receive domain clock.

Clock domain crossing FIFO

A high-speed parallel data communication approach overcomes data skewing concerns by concurrently transmitting data in a plurality of multiple-bit groups and, after receiving the concurrently-transmitted data, realigning skew-caused misalignments between the groups. In one particular example embodiment, for each group, an arrangement transfers the data in parallel and along with a clock signal for synchronizing digital data. The transferred digital data is synchronously collected via the clock signal for the group. At the receiving module, the data collected for each group is aligned using each group's dedicated clock signal. Skew across clock-domain groups is tolerated and overcome by processing the data and the skew first within each clock domain group, and then between groups.

Parallel data communication realignment of data sent in multiple groups

A communication protocol provides high-speed transfers of parallel data between an origination end and a destination end. The protocol involves regularly transmitting data from the origination end to the destination end, including transmitting idle data from the origination end when the destination end is busy and during periods when no commands, data or statuses are pending. When the destination end is not busy, data is sent from the origination end to the destination end by: sequentially transferring read or write commands and, according to a write protocol, pending write data; and transmitting idle packets during periods when no commands are pending. When the origination end is not busy, data is sent from the destination end to the origination end by: sequentially transferring pending end-of-write statuses; sequentially transferring pending read data and read statuses packets according to a read protocol during periods when no end-of-write statuses are pending; and transmitting idle packets during periods when no read data or read status are pending.

High-speed interchip interface protocol

In one example embodiment, a high-speed parallel-data communication approach transfers digital data in parallel from a first module to a second module over a communication channel including a plurality of parallel data-carrying lines and a clock path. The parallel bus lines are arranged in a plurality of groups, each of the groups including a plurality of data-carrying lines and a clock path adapted to carry a clock signal for synchronizing digital data carried from the first module to the second module. The sets of data are concurrently transferred using the groups of lines of the parallel bus, and at the second module and for each group, the transferred digital data is synchronously collected via the clock signal for the group. At the second module, the data collected for each group is aligned. By grouping the bus lines in groups with each group having its own clock domain, skew across clock-domain groups is tolerated and overcome by processing the data and the skew first within each clock domain group, and then between groups.

Parallel data communication having skew intolerant data groups

A rapid silicon processing arrangement significantly decreases the time from initial design to market introduction. Consistent with one embodiment of the present invention, the rapid silicon processing arrangement uses a deconfigurable and extendible reference-chip development platform that includes a programmable device such as an electronically reconfigurable gate array and an off-platform bus for communicating with external devices. The reference-chip development platform can be deconfigured by deselecting communicative activity by one or more of functional block macros. The external devices can be used with the reference-chip development platform to test a hardware representation of the synthesized subset of the functional block macros in the programmable device within the reference-chip development platform as extended by the off-platform bus. The approach significantly decreases the development time, from initial design to market introduction.

Method and arrangement for rapid silicon prototyping

In one example embodiment, data is transferred at high speeds over a parallel data bus without loss of data integrity by transferring the data encoded with the quantity of ones relatively the same as the quantity of zeroes. Consistent with one embodiment of the present invention, a bus-interface circuit encodes a set of X data bits into a set of Y data bits, where Y is greater than X. The encoding is implemented to approximately balance the number of ones and the number of zeroes in each set to be transmitted. A specific example application involves encoding the set of X data bits so that there is a balanced number of ones and zeroes in the set of Y data bits. In certain applications, the present invention is implemented to reduce current flow between transmitting and receiving modules and thereby reduce EMI, reduce the number of power pins required for the bus interface, and/or reduce the I/O delay and the skew from voltage sag in the signals passed over the parallel data bus.

Parallel communication based on balanced data-bit encoding

The timing characteristics of an integrated circuit design with an original combination-logic module can be potentially improved by moving an input signal with problematic timing in the original module so that it controls an output multiplexer in a revised module. The revised module includes two submodules. The first submodule provides the desired logic result where the late signal is low; the second submodule provides the desired logic result where the late signal is high. The multiplexer is controlled by the late signal so that its output is the desired logic result under steady-state conditions. If there are other input signals requiring timing advancement, the method can be reiterated. The method can be iterated until specifications are met or it is clear that the method cannot meet specifications by additional iterations.

Computer-implemented conversion of combination-logic module for improving timing characteristics of incorporating integrated circuit design

A method of selecting a cache design for a computer system begins with the making of a prototype module with a processor, a &ldquo;seed&rdquo; cache, and a trace detection module. The prototype module can be inserted within a system that includes main memory and peripherals. While an application program is run on the system, the communications between the processor and the seed cache are detected and compressed. The compressed detections are stored in a trace capture module and collectively define a trace of the program on the prototype module. The trace is then expanded and used to evaluate a candidate cache design. The expansion and evaluation can be iterated to evaluate many cache designs. The method can be used to pick the cache design with the best performance or as a foundation for performing a cost/performance comparison of the evaluated caches. In this method, a single prototype is used to generate an accurate trace that permits many alternative cache designs to be evaluated. This contrasts with methods that use cacheless models to develop less accurate traces and methods that allow only one cache design to be evaluated per prototype. In summary, the invention provides an accurate and efficient method of evaluating alternative cache designs.

Selecting a cache design for a computer system using a model with a seed cache to generate a trace

A computer system includes a RAM-based FIFO for buffering communications between a host processor and a remote serial-communications device. The FIFO provides for quadlet, doublet, and singlet transfer widths depending on the memory-mapped IO address asserted by the processor. Quadlet transfers can be implemented until the amount of data remaining to be transferred is less than four bytes. For each quadlet transfer, the read pointer, in the case of a read operation, or the write pointer, in the case of a write operation, is incremented by four. If two or three bytes of data remain after the quadlet transfers, a doublet transfer can be implemented; in this case, the appropriate pointer is incremented by two. Finally, if a byte of data remains after the quadlet transfers and a possible doublet transfer, then a singlet transfer is effected. In this case, the appropriate pointer is incremented by one. For example, 31 bytes of data in an 8&times;4-byte FIFO can be transferred in seven quadlet transfers, one doublet transfer, and one byte-wide transfer. The use of the wide transfers greatly reduces the processor overhead in servicing the FIFO, making more processor power available to concurrently running tasks and improving system performance overall.

FIFO system with variable-width interface to host processor

A method of designing a mask-programmable random-access read-only memory device begins with a step of assigning weightings to addresses according to their expected frequency of access. These weighting are used in a second step of determining for each sense amplifier, what is the low-power sense (inverted or uninverted) of the stored bits using that sense amplifier as an output. The third step involves storing the data in the low-power sense. The fourth step involves inverting the outputs for the data that is stored inverted. This can involve using sense inverting sense amplifiers for inverted data and sense preserving amplifiers for uninverted data. The method can result in memories in which some outputs are sense inverting while others are sense preserving. The result is a memory device with reduced power consumption relative to a comparable design not taking advantage of the relationship between data values and power consumption.

Binary data memory design with data stored in low-power sense

A method and arrangement passes data between two busses without needing conventional bridge-interface protocols. Consistent with one method embodiment of the present invention, data is passed between a first bus on a reference chip and an external bus using a two-way buffer arrangement between the external bus and the first bus. The method includes coupling a two-way buffer arrangement between the external bus and the first bus, determining which of the busses is the initiating bus, and in response to this determination, controlling the two-way buffer arrangement to asynchronously copy data through the two-way buffer arrangement from the initiating bus to the other bus, wherein data is passed automatically in response to its presence at the buffer arrangement without any clock cycle delays. An example application is directed to interfacing with a bus used for a rapid silicon processing chip.

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Crystal Lake, IL, United States of America

Timothy A Pontius