Silicon Laboratories Inc.

Skyworks Solutions, Inc.

Other

Timothy A Monk

Rajesh Thirugnanam

Douglas F Pastorello

Raghunandan Kolar Ranganathan

Krishnan Balakrishnan

Srisai Rao Seethamraju

William Anker

Michael Henderson Perrott

Aslamali A Rafi

Ping Lu

Michael Lu

A spur measurement system uses a first device with a spur cancellation circuit that cancel spurs responsive to a frequency control word identifying a spurious tone of interest. A device under test generates a clock signal and supplies the clock signal to the first device through an optional divider. The spur cancellation circuit in the first device generates sine and cosine weights at the spurious tone of interest as part of the spur cancellation process. A first magnitude of the spurious tone in a phase-locked loop in the first device is determined according to the sine and cosine weights and a second magnitude of the spurious tone in the clock signal is determined by the first magnitude divided by gains associated with the first device.

Spur cancellation for spur measurement

A clock product includes a time-to-digital converter responsive to an input clock signal, a reference clock signal, and a time-to-digital converter calibration signal. The time-to-digital converter includes a coarse time-to-digital converter and a fine time-to digital converter. The clock product includes a calibration circuit including a phase-locked loop. The calibration circuit is configured to generate the time-to-digital converter calibration signal. The clock product includes a controller configured to execute instructions that cause the phase-locked loop to generate an error signal for each possible value of a fine time code of a digital time code generated by the time-to-digital converter and to average the error signal over multiple clock cycles to generate an average error signal.

Calibration of a time-to-digital converter using a virtual phase-locked loop

A phase and frequency detector receives a reference clock signal with a period error and receives a feedback clock signal from a feedback divider. The feedback divider circuit divides a clock signal from a voltage controlled oscillator. The feedback divider divides by different divide values during odd and even cycles of the reference clock signal to cause the feedback clock signal to have a period error that substantially matches the period error of the reference clock signal. The divider values supplied to the feedback divider are determined, at least in part, by the period error of the reference clock signal.

Correction for period error in a reference clock signal

In at least one embodiment, a method includes generating a digital time code corresponding to an input clock signal using a time-to-digital converter responsive to a reference clock signal and a time-to-digital converter calibration signal. The method includes generating the time-to-digital converter calibration signal based on the digital time code. Generating the time-to-digital converter calibration signal includes generating a digital error signal based on the digital time code and an estimated digital time code, and adapting the time-to-digital converter calibration signal based on the digital error signal.

A clock generator includes an interpolative divider including a phase interpolator and a multi-modulus divider. The interpolative divider is configured to generate an output clock signal based on a clock signal, a control code, and a phase interpolator calibration signal. The clock generator includes a calibration circuit configured to generate the phase interpolator calibration signal based on the clock signal, the output clock signal and a phase interpolator code. The calibration circuit includes a phase-locked loop configured to generate a digital phase error signal based on a reference timestamp signal and a timestamp signal based on the clock signal and the output clock signal. The calibration circuit includes an adaptive loop configured to generate the phase interpolator calibration signal based on the digital phase error signal.

Calibration of an interpolative divider using a virtual phase-locked loop

A spur target frequency is periodically determined to cancel a spur using a spur cancellation circuit in a first phase-locked loop (PLL) in a system with at least a second PLL that is in lock with the first PLL. The spur target frequency is periodically determined utilizing divide ratios of the first PLL and the second PLL to determine the updated spur target frequency. As one or more of the divide ratios change, the spur frequency changes and the spur target frequency is updated to reflect the change.

Spur cancellation in a PLL system with an automatically updated target spur frequency

A spur cancellation circuit uses low cost multipliers in a correlation circuit. Each low cost multiplier multiplies a value of a sense node by a representation of a sinusoid and supplies a multiplication result. A compare circuit compares the sinusoid to one or more threshold values and supplies a compare indication. A multiplexer selects between two or more inputs including a positive value of the sense node and a negative value of the sense node, based on the compare result. A single threshold at zero converts the sinusoid to a square wave and the multiplexer supplies either the positive value or the negative value, which is equivalent to multiplying the value at the sense node by 1 or &#x2212;1 depending on the sign of the sinusoid. Two thresholds may be used to represent the sinusoid with three values, the positive value, the negative value, or zero.

Spur canceller with multiplier-less correlator

A spur cancellation circuit receives a target spur frequency indicative of a frequency of a spur to be canceled and supplies a spur cancellation signal based on the frequency. A frequency tracking circuit tracks a change in the frequency of the spur to be canceled based on a change in phase of the spur cancellation signal and generates an updated target spur frequency based on the change in the frequency of the spur.

Spur cancellation with adaptive frequency tracking

A chip having output synchronization includes a phase detector for receiving an external reference clock signal, an input delay path coupled to an output of the phase detector and having an output for providing an internal reference clock signal, an output delay path coupled to the output of the input delay path and having an output coupled to a feedback input of the phase detector, a phase adjustment circuit having a first input coupled to the output of the input delay path, a second input for receiving a local clock signal, and an output coupled to the control input of the input delay path, and a synchronization capture circuit having a first input coupled to the output of said input delay path, a second input for receiving the local clock signal, a third input for receiving a synchronization signal, and an output for providing a synchronization trigger signal.

Metastable-free output synchronization for multiple-chip systems and the like

A noise-shaping signed digital-to-analog converter is described. A method includes selectively enabling a first sequence of unit elements of a plurality of unit elements of a digital-to-analog converter to convert a signed digital code to a plurality of analog signals in response to a plurality of control signals. Individual control signals of the plurality of control signals and individual analog signals of the plurality of analog signals correspond to respective unit elements of the plurality of unit elements. The method includes generating the plurality of control signals based on a pointer, a magnitude of the signed digital code, and a sign of the signed digital code. The method may include combining the plurality of analog signals with an output of a phase/frequency detector and charge pump in a phase-locked loop. The signed digital code may be an error signal based on a predetermined divide ratio of the phase-locked loop.

Noise shaping signed digital-to-analog converter

Two sets of information (phase and cycle count) that are created asynchronously in a voltage controlled oscillator based analog-to-digital converter. A third set of information is created that is a delayed cycle count. The three sets of information are used to determine the proper alignment of the phase and the cycle count.

Aligning asynchronous signals by time shifting information

A feedback loop includes an oscillator-based analog-to-digital converter configured to convert an analog signal to a first digital value and a second digital value. The oscillator-based analog-to-digital converter includes a first oscillator having a first oscillation frequency configured to generate a first digital value based on a first signal component of the analog signal. The oscillator-based analog-to-digital converter includes a second oscillator having a second oscillation frequency configured to generate a second digital value based on a second signal component of the analog signal. The first and second signal components are complementary signal components. The feedback loop includes a combiner configured to generate a digital value based on the first digital value, the second digital value, and an offset code. The offset code has a value that increases a difference between the first oscillation frequency and the second oscillation frequency.

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Hudson, NH, United States of America

Timothy A Monk