Honeywell Information Systems Inc.

Timothy A Andrews

Chester M Nibby, Jr

Reeni Goldin

A remapping method and apparatus is employed by a memory controller system which includes a microprocessing section which couples to a memory section. The memory section includes a partially good bulk random access memory constructed from a plurality of bit wide chips containing a predefined small number of row or column faults randomly distributed. System columns of chips are organized into a plurality of groups or slices, each of which provide a different predetermined portion of the locations within the partially good bulk memory. A defective-free memory having substantially less capacity is similarly organized. Both memories couple to a static memory which is remapped under the control of the microprocessing section. Prior to remapping, the microprocessing section generates a 'slice bit map' indicating the results of testing successive bit groups/slices within the bulk memory locations. Thereafter, the microprocessor section interprets the 'slice bit map' and assigns column addresses in the static memory locations designating locations within the defect-free memory. The assignment is carried out in a predetermined manner according to fault category to maximize the use of all of the groups of bit locations within each defect free memory location thereby making storage available for remapping new faults.

Remap method and apparatus for a memory system which uses partially good

A memory controller includes a partial defective bulk random access memory having a number of word locations constructed from a plurality of bit wide chips containing a predefined small number of random row or column faults. System columns of chips are organized into a plurality of groups, each group providing a different predetermined portion of the number of word locations. A defect-free memory system having substantially less capacity is similarly organized. Both memories couple to a static memory which stores column addresses associated with good memory locations and slice bit codes specifying the operational status of corresponding bit groups of word locations within both memories. During operation, read/write control circuits read and write valid words from group of bit locations from locations of both memories specified by slice bit codes.

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Arlington, MA, United States of America

Timothy A Andrews