Hewlett-packard Development Company, L.P.

Intel Corporation

Timothe Litt

Richard Eugene Kessler

Kaladhar Radhakrishnan

Cengiz Ahmet Palanduz

Thomas Frederick Hummel

Larry Binder

Sriram Dattaguru

David Bach

Christopher C Jones

Chris Jones

Dave Bach

A ceramic package substrate has a recess. This allows a device in that recess to be close to a die attached to the substrate's top side, for better performance. The device may be an array capacitor, an in-silicon voltage regulator, or another device or devices.

Ceramic package substrate with recessed device

In some embodiments, an individual sub-assembly containing a ceramic interposer, silicon voltage regulator, and array capacitor is presented. In this regard, an apparatus is introduced having a table-shaped ceramic interposer containing conductive traces, a silicon voltage regulator coupled with contacts on a first surface of the ceramic interposer, and an array capacitor coupled with contacts on a second surface of the ceramic interposer. Other embodiments are also disclosed and claimed.

Individual sub-assembly containing a ceramic interposer, silicon voltage regulator, and array capacitor

A system having multiple on-chip logic analyzers (OCLA), each on-chip logic analyzer includes one or more word recognizers. The word recognizer includes a great deal of flexibility for the user, while being capable of implementation with very few gates. The word recognizer includes a Boolean logic portion in which a plurality of conditions can be dynamically segregated into a mutually exclusive set of groups. The conditions in each group are combined by means of a single Boolean function that is programmable. The resultant term (or product) from each group is combined with those of the other groups by a fixed selection of Boolean functions. The output of the Boolean logic section is provided to a counter/timer.

Efficient word recognizer for a logic analyzer

A system is disclosed in which an on-chip logic analyzer (OCLA) is included in an integrated circuit, such as a microprocessor. During debug modes, one or more sets of an on-chip cache memory are disabled from use by other circuitry in the integrated circuit, and reserved exclusively for use by the OCLA. Data stored in the reserved cache set can then be read out by the OCLA, and placed in a register that can be accessed by other logic internal or external to the integrated circuit. If the integrated circuit is operating under normal mode, the cache memory set can be used in conventional fashion by other circuitry with in the integrated circuit to enhance performance.

Method and apparatus for efficiently implementing trace and/or logic analysis mechanisms on a processor chip

A system is disclosed in which an on-chip logic analyzer (OCLA) includes timestamp logic capable of providing clock cycle resolution of data entries using a relatively small number of bits. The timestamp logic includes a counter that is reset each time a store operation occurs. The counter counts the number of clock cycles since the previous store operation, and if enabled by the user, provides a binary signal to the memory that indicates the number of clock cycles since the previous store operation, which the memory stores with the state data. If the counter overflows before a store operation is requested, the timestamp logic may force a store operation so that the time between stores can be determined.

Method and apparatus for managing timestamps when storing data

An output port for an integrated circuit includes a bandwidth manager for assisting in the off-loading of internal state data during debug periods. The bandwidth manager operates to take internal state data at its normal frequency, and outputs at least the most important portions of that data to external logic. During periods when the output port is able to keep up with the internal sources being sampled, the bandwidth manager will cause all of the state data to be transmitted. If the output port becomes saturated, the bandwidth manager will select the most important portions of the internal state data to be transmitted off-chip, and will drop the less important information. The bandwidth manager is configured to operate dynamically based on the ability of the output port to keep up with the data being generated by the internal sources. The bandwidth manager determines the importance of data based on principles underlying the structure of packets, rather than on detailed parsing of packets, and without relying on knowledge of packet semantics.

Method and apparatus for efficiently managing bandwidth of a debug data output port or buffer

A system is disclosed in which an on-chip logic analyzer (OCLA) includes a loop detector logic which receives incoming program counter (PC) data and detects when software loops exist. When a software loop is detected, the loop detector may be configured to store the first loop in memory, while all subsequent iterations are not stored, thus saving space in memory which would otherwise be consumed. The loop detector comprises a content addressable memory (CAM) which is enabled by a user programmed signal. The CAM may be configured with a programmable mask to determine which bits of the incoming PC data to compare with the CAM entries. The depth of the CAM also is programmable, to permit the CAM to be adjusted to cover the number of instructions in a loop.

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Southborough, MA, United States of America

Timothe Litt