Freescale Semiconductor,inc.

Nxp USA, Inc.

Tim V Pham

Michael B McShane

Perry H Pelley

Trent Uehling

George R Leal

James R Guajardo

Leo M Higgins, Iii

Andrew Christopher Russell

Tab Allen Stephens

Chee Seng Foong

Min Ding

Derek S Swanson

Gary J Kovar

Patrick B Cochran

The dies of a stacked die IC are tested and, in response to detection of a defect at one of the dies, the type of defect is identified. If the defect is identified as a defective module repairable at the die itself, a redundant module of the die is used to replace the functionality of the defective module. If the defect is identified as one that is not repairable, a replacement die in the die stack is used to replace the functionality of the defective die.

Defective die replacement in a die stack

The dies of a stacked die integrated circuit (IC) employ the address bus to indicate the particular die, or set of dies, targeted by data on a data bus. During manufacture of the stacked die IC, the IC is programmed with information indicating a width of the address bus. During operation, each die addresses the other dies with addresses having the corresponding width based on this programmed information.

Die stack address bus having a programmable width

A method and apparatus are provided for manufacturing a lead frame based thermally enhanced flip chip package with an exposed heat spreader lid array () designed for direct attachment to an array of integrated circuit die () by including a thermal interface adhesion layer () to each die () and encapsulating the attached heat spreader lid array () and array of integrated circuit die () with mold compound () except for planar upper lid surfaces of the heat spreader lids ().

Matrix lid heatspreader for flip chip package

A low profile strip dual in-line memory module () includes a passive interposer support structure () with patterned openings (-) formed between opposing top and bottom surfaces, a plurality of memory chips (D-D) attached to the top and bottom surfaces, and vertical solder ball conductors () extending through the patterned openings to electrically connect the plurality of memory chips, where each memory chip has an attachment surface facing the passive interposer structure and a patterned array of horizontal conductors (e.g.,-) formed on the attachment surface with contact pads electrically connected to the plurality of vertical conductors to define at least one bus conductor that is electrically connected to each memory die in the first and second plurality of memory die.

Thin low profile strip dual in-line memory module

A first semiconductor device die is provided having a bottom edge incorporating a notch structure that allows sufficient height and width clearance for a wire bond connected to a bond pad on an active surface of a second semiconductor device die upon which the first semiconductor device die is stacked. Use of such notch structures reduces a height of a stack incorporating the first and second semiconductor device die, thereby also reducing a thickness of a semiconductor device package incorporating the stack.

Wirebond recess for stacked die

A microelectronic device package including a package substrate, microelectronic component disposed on a first surface of a first portion of the substrate, and encapsulant material surrounding the microelectronic electronic component. An exposed surface of the first portion of the substrate is exposed through an opening in a first major surface of the encapsulant material. The exposed surface of the first portion has an edge. Encapsulant material is adjacent to the edge at the first major surface. The exposed surface is opposite the first surface. A stress relief feature located in one of the first major surface or a second major surface of the encapsulant material. The second major surface is opposite the first major surface. The stress relief feature reduces an amount of the encapsulant material and is 1 mm or less of a plane of the edge of the exposed surface. The plane is generally perpendicular to the exposed surface.

Package encapsulant relief feature

Edge coupling of semiconductor dies. In some embodiments, a semiconductor device may include a first semiconductor die, a second semiconductor die disposed in a face-to-face configuration with respect to the first semiconductor die, and an interposer arranged between the first semiconductor and second semiconductor dies, the interposer having an edge detent configured to allow an electrical coupling between the first and second semiconductor dies. In other embodiments, a method may include coupling a first semiconductor die to a surface of an interposer where an edge of the interposer includes detents and the first semiconductor die includes a first pad aligned with a first detent, coupling a second semiconductor die to an opposite surface of the interposer where the first and second semiconductor dies are in a face-to-face configuration and the second semiconductor die includes a second pad aligned with a second detent, and coupling the first and second pads together.

Edge coupling of semiconductor dies

An integrated circuit package includes a substrate having a heat conducting portion integrally formed with a heat dissipating portion. First and second integrated circuit dies are mounted to opposite sides of the heat conducting portion of the substrate. The first and second integrated circuit dies may each be packaged as flip-chip configurations. Electrical connections between contact pads on the first and second integrated circuit dies may be formed through openings formed in the heat conducting portion of the substrate. The heat dissipating portion may be positioned externally from a location between the first and second integrated circuit dies so that it dissipates heat away from the integrated circuit package into the surrounding environment.

Heat conductive substrate for integrated circuit package

A first set of electrically conductive cladding is disposed on an inner section of one external side of a package substrate. The first set electrically conductive cladding is fabricated with a first solder compound. A second set of electrically conductive cladding is disposed on an outer section of the one external side of the substrate. The second set of electrically conductive cladding consists of a second solder compound. The outer section can be farther away from a center of the one external side of the substrate than the inner section. During a reflow process, the first and second solder compounds are configured to become completely molten when heated and the first solder compound solidifies at a higher temperature during cool down than the second solder compound.

Methods and structures for reducing stress on die assembly

A semiconductor device includes a semiconductor die having a first major surface and a second major surface opposite the first major surface, a first minor surface and a second minor surface opposite the first minor surface, a plurality of contact pads on the first major surface, and a notch which extends from the first minor surface and the second major surface into the semiconductor die. The notch has a notch depth measured from the second major surface into the semiconductor die, wherein the notch depth is less than a thickness of the semiconductor die, and a notch length measured from the first minor surface into the semiconductor die, wherein the notch length is less than a length of the semiconductor die measured between the first and second minor surfaces. The device includes a lead having a first end in the notch, and an encapsulant over the first major surface.

Using an integrated circuit die configuration for package height reduction

A fluid cooled semiconductor die package includes a package support substrate with a die mounting surface and an opposite package mounting surface. The package support substrate has external connector solder deposits on respective external connector pads of the package mounting surface, and a package fluid inlet duct and a package fluid outlet duct each providing fluid communication between the die mounting surface and package mounting surface. A semiconductor die is mounted on the die mounting surface. The die has external terminals electrically connected to the external connector pads. An inlet solder deposit is soldered to an inlet pad of the package mounting surface. The inlet pad surrounds an entrance of the fluid inlet duct. An outlet solder deposit is soldered to an outlet pad of the package mounting surface. The outlet pad surrounds an exit of the package fluid inlet duct.

Fluid cooled semiconductor die package

A semiconductor device is provided which comprises a substrate () having a plurality of bond pads () disposed thereon. Each bond pad has a major axis and a minor axis in a direction parallel to the substrate, and the ratio of the major axis to the minor axis increases with the distance of a bond pad from the center of the substrate.

Dynamic pad size to reduce solder fatigue

A packaged array () having a temporary substrate () is used to test a plurality of semiconductor devices (). In one embodiment, the temporary substrate () is an adhesive substrate, such as tape. A support structure () may lie over the temporary substrate () or be within the temporary substrate (). The plurality of semiconductor devices () lie within an array (or) and may be tested in parallel. One array or a multiple number of arrays may lie on the packaged array ().

Growing community of inventors

Austin, TX, United States of America

Tim V Pham