Altera Corporation

Intel Corporation

Tim Tri Hoang

Sergey Yuryevich Shumarayev

Wilson Wong

Thungoc M Tran

Weiqi Ding

Rakesh H Patel

Simardeep Maangat

Tin H Lai

Kazi Asaduzzaman

Allen K Chan

Tien Duc Pham

Richard G Cliff

Sangeeta Raman

Vinh Van Ho

Shou-Po Shih

Yanjing Ke

Nam V Nguyen

Ramanand Venkata

Wanli Chang

William W Bereza

Leon Zheng

Neville Carvalho

Chong H Lee

Kyung Suk Oh

In Whan Kim

Ning Xue

Henry Y Lui

Arch Zaliznyak

Kumara Tharmalingam

Michael Menghui Zheng

Yujeong Shim

Toan Thanh Nguyen

Mian Z Smith

Xiong Liu

Doris Po Ching Chan

Kang-Wei Lai

Richard Hernandez

Kok Siang Tan

Bruce B Pedersen

Bonnie I Wang

David Wolk Mendel

Hae-Chang Lee

Dinesh D Patil

Ninh D Ngo

Rabindranath Balasubramanian

Jie Shen

Jakob Raymond Jones

Mei Luo

Andy Turudic

Sriram Narayan

Surinder Singh

Allan Thomas Davidson

Binh Ton

Lawrence David Smith

Gopi Krishnamurthy

Vishal Giridharan

Malik Kabani

Van Ton-That

Sunitha Chandra

Kalyan Kankipati

Haidang Lin

Seungmyon Park

Ben Chunben Wang

An integrated circuit having a transmitter is provided. The transmitter may include a serializer, a driver, and an associated calibration circuit. The calibration circuit may include a detector and a control circuit. The control circuit may output a first control signal for selectively configuring the serializer to inject test data and may also output a second control signal for selectively inverting the input polarity of the detector. The control circuit may configure the transmitter in at least four different modes by adjusting the first and second control signals. In each of the four modes, the control circuit may sweep a clock duty cycle correction (DCC) setting that controls only the serializer until the detector flips. Codes generated in this way may be used to compute calibrated settings that mitigates both clock and data duty cycle distortion for the transmitted data.

Methods and apparatus for performing clock and data duty cycle correction in a high-speed link

The present disclosure provides apparatus and methods for the calibration of analog circuitry on an integrated circuit. One embodiment relates to a method of calibrating analog circuitry within an integrated circuit. A microcontroller that is embedded in the integrated circuit is booted up. A reset control signal is sent to reset an analog circuit in the integrated circuit, and a response signal for the analog circuit is monitored by the microcontroller. Based on the response signal, a calibration parameter for the analog circuit is determined, and the analog circuit isconfigured using the calibration parameter. Other embodiments, aspects and features are also disclosed.

Apparatus and methods for calibrating analog circuitry in an integrated circuit

A computer-implemented method includes receiving a first circuit design for an integrated circuit device, determining when multiple power-drawing events are to occur at substantially the same time via one or more circuitry components of the integrated circuit device, which would have a disruptive effect on a power distribution network of the integrated circuit device, based on the first circuit design, and generating logic that schedules the more than one event so that the more than one event do not occur simultaneously. The logic is included in an event sequencer. The method also includes inserting the event sequencer into the first circuit design during compilation to create a second circuit design and outputting the second circuit design to be implemented on the integrated circuit device.

Reset sequencing for reducing noise on a power distribution network

The present disclosure provides apparatus and methods for the calibration of analog circuitry on an integrated circuit. One embodiment relates to a method of calibrating analog circuitry within an integrated circuit. A microcontroller that is embedded in the integrated circuit is booted up. A reset control signal is sent to reset an analog circuit in the integrated circuit, and a response signal for the analog circuit is monitored by the microcontroller. Based on the response signal, a calibration parameter for the analog circuit is determined, and the analog circuit is configured using the calibration parameter. Other embodiments, aspects and features are also disclosed.

Systems and methods are provided for adjusting gain of a receiver. Adaptation circuitry is operable to identify, based on a matrix representation of a receiver's output generated from horizontal and vertical sweeps of the receiver's output, an eye opening of the receiver's output. The adaptation circuitry is also operable to determine whether a size of the eye opening needs to be changed. When it is determined that the size of the eye opening needs to be changed, the adaptation circuitry is operable to generate a digital signal to change a gain setting of the receiver. When the signal at the receiver's output is under-equalized, the AC gain of the receiver is increased. When the signal at the receiver's output is over-equalized, the AC gain of the receiver is decreased.

Digital equalizer adaptation using on-die instrument

Systems and methods for reducing jitter due to power supply noise in an integrated circuit by drawing additional current. The additional current causes the total current to generally have a frequency higher than a resonant frequency of the integrated circuit and/or a power distribution network of the integrated circuit. A power distribution network may supply power to components of an integrated circuit, and data driver circuitry may draw first current to drive a serial data signal generated from a parallel data signal. Compensation circuitry may receive the parallel data signal and draw second current at times when the compensation circuitry determines data driver circuitry is not drawing the first current based on the parallel data signal, thereby causing a net of the first and second current to be higher than a resonant frequency range of the integrated circuit device and/or a component of the integrated circuit device.

Systems and methods for reducing power supply noise or jitter

A driver circuit drives data to an output based on an input data signal in a transmission mode. The driver circuit includes transistors. A comparator generates a comparison output in a calibration mode based on a reference signal and a signal at the output of the driver circuit. A calibration control circuit adjusts an equivalent resistance of the transistors in the driver circuit based on the comparison output in the calibration mode. The equivalent resistance of the transistors in the driver circuit can be adjusted to support the transmission of data according to multiple different data transmission protocols using transmission links having different characteristic impedances. The equivalent resistance of the transistors in the driver circuit can also be adjusted to compensate for resistance in the package routing conductors and/or to compensate for parasitic resistance.

Circuits and methods for impedance calibration

One embodiment relates to an integrated circuit including multiple PMA modules, a plurality of multiple-purpose PLLs, multiple reference clock signal inputs, and a programmable clock network. Another embodiment relates to a fracture-able PLL circuit. The fracture-able PLL circuit includes a first phase-locked loop circuit generating a first frequency output, a second phase-locked loop circuit; arranged to generate a second frequency output, and a plurality of shared output resources. Reconfigurable circuitry is arranged so that either of the first and second frequency outputs is receivable by each of the plurality of shared output resources. Another embodiment relates to an integrated circuit including a first strip of PLL circuits on a first side of the integrated circuit, and a second strip of PLL circuits on a second side of the integrated circuit which is opposite from the first side. Other embodiments and features are also disclosed.

Phase-locked loop architecture and clock distribution system

A transceiver system with reduced latency uncertainty is described. In one implementation, the transceiver system has a word aligner latency uncertainty of zero. In another implementation, the transceiver system has a receiver-to-transmitter transfer latency uncertainty of zero. In yet another implementation, the transceiver system has a word aligner latency uncertainty of zero and a receiver-to-transmitter transfer latency uncertainty of zero. In one specific implementation, the receiver-to-transmitter transfer latency uncertainty is eliminated by using the transmitter parallel clock as a feedback signal in the transmitter phase locked loop (PLL). In one implementation, this is achieved by optionally making the transmitter divider, which generates the transmitter parallel clock, part of the feedback path of the transmitter PLL. In one implementation, the word aligner latency uncertainty is eliminated by using a bit slipper to slip bits in such a way so that the total delay due to the word alignment and bit slipping is constant for all phases of the recovered clock. This allows for having a fixed and known latency between the receipt and transmission of bits for all phases of parallelization by the deserializer. In one specific implementation, the total delay due to the bit shifting by the word aligner and the bit slipping by the bit slipper is zero since the bit slipper slips bits so as to compensate for the bit shifting that was performed by the word aligner.

Transceiver system with reduced latency uncertainty

In one embodiment, an integrated circuit current mirror circuit is disclosed. The integrated circuit current mirror circuit includes a reference circuit, an output circuit and a mode selector circuit. The reference circuit includes an input terminal that receives a reference current. The output circuit generates an output current that is proportional to the reference current. The output circuit is coupled to a load circuit. The output current is provided to the load circuit. The mode selector circuit is coupled to the reference circuit and the output circuit. The mode selector circuit receives a plurality of mode control signals having different voltage levels. The mode selector circuit selects one of the mode control signals. The selected mode control signal is routed to the reference circuit and the output circuit to place the current mirror circuit in a desired mode.

Multimode current mirror circuitry

One embodiment relates to an integrated circuit including multiple PMA modules, a plurality of multiple-purpose PLLs, multiple reference clock signal inputs, and a programmable clock network. Each PMA module includes multiple CDR circuits, receives multiple serial data signals, and outputs data from those signals in parallel form. The programmable clock network allows the reference clock signals to be selectively shared by the PMA modules and the multiple-purpose PLLs. Another embodiment relates to a method of providing clock signals for multiple purposes in an integrated circuit. Clock signals are generated by a plurality of multiple-purpose PLLs and are selectively distributed to PMA modules arranged at a side of the integrated circuit and to logic circuitry arranged in a core section of the integrated circuit. The clock signals are used by circuitry in the PMA modules for supporting a plurality of data communications channels. Other embodiments and features are also disclosed.

A pre-emphasis circuitry that includes (1) a pre-emphasis voltage variation compensation (PVVC) engine having a transition detection circuit and (2) a compensation driver coupled to the PVVC engine is described. In one embodiment, the compensation driver reduces data dependent voltage variations in pre-emphasis provided by the pre-emphasis circuitry. In one embodiment, in response to a predetermined data pattern detected by the PVVC engine, the compensation driver provides an additional boost to performance critical capacitive nodes of the pre-emphasis circuitry. The additional boost causes the performance critical capacitive nodes to charge or discharge more rapidly. In one embodiment, the PVVC engine further includes a digital finite impulse response (FIR) filter coupled to the transition detection circuit. Also, in one embodiment, the PVVC engine further includes an FIR delay circuit coupled to the digital FIR filter and a synchronizer circuit coupled to the digital FIR filter and the FIR delay circuit, where the FIR delay circuit introduces latency to match-delay produced by the transition detection circuit and the synchronizer circuit synchronizes data to be sent to the main driver, the pre-emphasis driver, and the compensation driver.

Pre-emphasis circuitry including a pre-emphasis voltage variation compensation engine

Growing community of inventors

San Jose, CA, United States of America

Tim Tri Hoang