Advanced Micro Devices Corporation

Spansion Llc.

Cypress Semiconductor Corporation

Monterey Research, LLC

Tim Thurgate

Shenqing Fang

Kuo-Tung Chang

Youseok Suh

Hidehiko Shiraiwa

Chih-Yuh Yang

Meng Ding

Amol Ramesh Joshi

Allison Holbrook

David H Matsumoto

Lovejeet Singh

Hapreet Sachar

Bharath Rangarajan

Sameer S Haddad

Yu Nan Sun

Richard M Fastow

Scott D Luning

Lee Edward Cleveland

Darlene G Hamilton

Narbeh Derhacobian

Ravi S Sunkavalli

Chun Chen

Emi Ishida

Stephen Keetai Park

Harpreet Kaur Sachar

Di Li

Concetta E Riccobene

Nga-Ching Wong

Janet S Y Wang

Tung-Sheng Chen

Michael K Han

Shenging Fang

A method for fabricating a memory device with a self-aligned trap layer and rounded active region corners is disclosed. In the present invention, an STI process is performed before any of the charge-trapping and top-level layers are formed. Immediately after the STI process, the sharp corners of the active regions are exposed. Because these sharp corners are exposed at this time, they are available to be rounded through any number of known rounding techniques. Rounding the corners improves the performance characteristics of the memory device. Subsequent to the rounding process, the charge-trapping structure and other layers can be formed by a self-aligned process.

System and method for manufacturing self-aligned STI with single poly

A method and apparatus for continuously rounded charge trapping layer formation in a flash memory device. The memory device includes a semiconductor layer, including a source/drain region. An isolation region is disposed adjacent to the source/drain region. A first insulator is disposed above the source/drain region. A charge trapping layer is disposed within the first insulator, wherein the charge trapping layer comprises a bulk portion and a first tip and a second tip on either side of said bulk portion, wherein said charge trapping layer extends beyond the width of the source/drain region. A second insulator is disposed above the charge trapping layer. A polysilicon gate structure is disposed above the second insulator, wherein a width of said control gate is wider than the width of said source/drain region.

Apparatus and method for rounded ONO formation in a flash memory device

A process for forming tilted edge wordline implants is disclosed. The process includes forming a first drain implant in a substrate, forming a first tilted implant in a substrate adjacent a first edge wordline to supplement said first drain implant where the first tilted implant is provided at a tilt angle from a first direction and forming a second tilted implant in the substrate adjacent a second edge wordline to supplement another first drain implant where the second tilted implant is provided at a tilt angle from a second direction. A second drain implant is formed in the substrate.

Process for forming edge wordline implants adjacent edge wordlines

Self-aligned STI with single poly for manufacturing a flash memory device

A method for fabricating a memory device with a self-aligned trap layer which is optimized for scaling is disclosed. In the present invention, a non-conformal oxide is deposited over the charge trapping layer to form a thick oxide on top of the core source/drain region and a pinch off and a void at the top of the STI trench. An etch is performed on the pinch-off oxide and the thin oxide on the trapping layer on the STI oxide. The trapping layer is then partially etched between the core cells. A dip-off of the oxide on the trapping layer is performed. And a top oxide is formed. The top oxide converts the remaining trap layer to oxide and thus isolate the trap layer.

Self-aligned patterning method by using non-conformal film and etch back for flash memory and other semiconductur applications

Self-aligned patterning method by using non-conformal film and etch back for flash memory and other semiconductor applications

A system and methodology is provided for programming first and second bits of a memory array of dual bit memory cells at a substantially high delta VT. The substantially higher VT assures that the memory array will maintain programmed data and erase data consistently after higher temperature stresses and/or customer operation over substantial periods of time. At a substantially higher delta VT, programming of the first bit of the memory cell causes the second bit to program harder and faster due to the shorter channel length. Therefore, the present invention employs selected gate and drain voltages and programming pulse widths during programming of the first and second bit that assures a controlled first bit VT and slows down programming of the second bit. Furthermore, the selected programming parameters keep the programming times short without degrading charge loss.

Charge injection

A method is provided for accurately determining the junction depth of silicon-on-insulator (SOI) devices. Embodiments include determining the junction depth in an SOI device under inspection by measuring the threshold voltage of its &ldquo;bottom transistor&rdquo; formed by its source and drain regions together with its substrate acting as a gate. The threshold voltage of the bottom transistor of an SOI device varies with its junction depth in a predictable way. Thus, the junction depth of the inspected device is determined by comparing its bottom transistor threshold voltage with the bottom transistor threshold voltage of corresponding reference SOI devices of known junction depth to find a match. For example, simulated SOI devices with the same characteristics as the inspected device, whose junction depth and bottom transistor threshold voltages have been previously calculated, are used as a &ldquo;reference library&rdquo;. If the bottom transistor threshold voltage of the inspected device has about the same value as that of a particular one of the reference devices, then the inspected device has the junction depth of that particular reference device. Thus, junction depth of the inspected SOI device is accurately determined by a simple electrical measurement of threshold voltage.

Method for measuring source and drain junction depth in silicon on insulator technology

A method of erasing a flash memory device that improves reliability and reduces the decrease in erase speed. The state of erasure is determined either during an erase phase or a verify phase and the information is fedback to a controller that adjusts the erase vertical electrical field that is to be applied to the array. The vertical electrical field is adjusted by changing the gate voltage, the well voltage or changing both simultaneously.

Feedback method to optimize electric field during channel erase of flash memory devices

A narrow groove is formed over a substrate. To form such a narrow groove, a first material is formed over a substrate, the first material having a sidewall. A spacer is formed abutting the sidewall. Subsequently a second material is formed adjacent to the spacer. The spacer is removed leaving a groove between the first material and second material. In one embodiment, the groove is filled with material for a narrow feature, such as a gate, and the first material and second material are removed. As a result a gate or other narrow feature is formed having a length defined by the width of a spacer. In another embodiment, an implant is performed through the small groove, resulting in a small localized implant.

Method to form narrow structure using double-damascene process

A process for fabricating an MNOS device includes the steps of forming a hardmask containing at least first and second openings over a core array area of a semiconductor substrate. An angle doping process is carried out to form halo regions in precise locations within the substrate at the edges of the first and second openings in the hardmask. Another doping process is carried out to form buried bit-lines in the substrate using the hardmask as a doping mask. Once the halo regions and the buried bit-lines are formed, the hardmask is removed and a composite dielectric layer is formed overlying the substrate. A gate layer is deposited to overlie the composite dielectric layer, and an etching process is carried out to form a control gate electrode and a charge storage electrode in the MNOS device

Process for fabricating an MNOS flash memory device

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Sunnyvale, CA, United States of America

Tim Thurgate