Quantum Corporation

Other

Tim R Glassburn

John Welsford Brooks

Bruce R Peterson

James A Henson

Richard J Blackborow

Jeffery H Appelbaum

James H Do

James P McGrath

Michael L Raab

Faheem Dani

Garrick Yeung

An improved disk drive architecture includes a microcontroller interface circuit connected between a drive microcontroller and a buffer controller. The microcontroller interface circuit includes address mapping registers for mapping at least one predetermined portion of directly addressable memory of the microcontroller to address locations of the drive's cache buffer. The buffer controller circuit includes an access arbitration circuit for arbitrating requests for access to the cache buffer by the drive's data sequencer, the drive's host interface controller and the drive's microcontroller. A microcontroller wait state generator responds to the access arbitration circuit by generating and applying a wait state sequence to the microcontroller until a request it makes for access to the cache buffer can be executed.

Shared memory array for data block and control program storage in disk

A high capacity micro-Winchester disk drive is capable of storing approximately 120 megabytes of user data on each storage disk. A digital bus interface connects to data, control and status lines from a host computer, and a cache memory defines a plurality of programmable memory segments for disk data, host data and microcontroller data. The cache memory controller enables read-ahead, write-ahead, and automatic multiple block read and write operations to occur between the disk drive and the host without intervention of the disk drive's embedded microcontroller.

Micro-winchester disk drive having on-board segmented cache memory

A mass storage subsystem is connectable to a host computer via a host adapter and includes a subsystem bus extending from the host adapter to at least one base unit and a removable disk drive cartridge for use with the base unit. A control signal path extends between the base unit and the removable disk drive cartridge when it is installed and connected within the base unit. The disk drive cartridge includes a housing, at least one storage disk rotatably mounted within the housing, at least one data transducer head within the housing and positionable by a head positioner at selected concentric data storage tracks defined on a storage surface of the storage disk. A bus interface circuit is provided for directly connecting to the subsystem bus when the cartridge is installed and connected within the base unit, and a cartridge controller is provided for controlling operations of the bus interface circuit and the head positioner and for communicating with the base unit via the control signal path. The base unit comprises a disk cartridge receiving structure for receiving and connecting the disk drive cartridge, a stand-in interface circuit connected to the subsystem bus means for presenting an active and 'drive not ready' disk cartridge appearance to the subsystem bus when the disk drive cartridge is not installed and connected within the base unit, and a base unit controller including a cartridge control for controlling operations of the disk cartridge receiving structure, and a stand-in interface control for communicating with the cartridge controller via the control signal path and for thereupon controlling stand-in operation of the stand-in interface circuit.

Electronic hot connection of disk drive module to computer peripheral bus

A method divides a recurrent digital clocking signal into a quotient digital signal having a substantially symmetrical duty cycle within a range of programmable quotients, the quotients being selectable in single increments of the recurrent digital clocking signal within a range as selected by a divisor. The method includes the steps of loading the divisor from a source into a down counter clocked by the recurrent digital clocking signal; down counting from the divisor to zero with the down counter in synchronism with the recurrent digital clocking signal; setting a bistable latch to a first state of synchronism with a beginning of down counting from the divisor, the bistable latch for putting out the quotient digital signal; dividing the divisor by two to provide a half-count value; comparing the half-count value with a count reached by the down counter and generating a compare true signal upon detected equivalence of the half-count value and the count reached; and, setting the bistable latch to a second state opposite the first state in synchronism with the compare true signal. As one aspect of this invention the foregoing steps are continuously repeated every time the step of down counting reaches zero.

High resolution symmetrical divider circuit

Growing community of inventors

Milpitas, CA, United States of America

Tim R Glassburn