Microchip Technology Inc.

Tim Phoenix

Igor Wojewoda

Stephen Bowling

Yong Yuenyongsgool

Andreas Reiter

Gaurang Kavaiya

Anton Alkhimenok

Pavan Kumar Bandarupalli

A microcontroller may include a DMA controller, a pattern matching circuit and a memory. The DMA controller may read a first descriptor word in the memory at a location addressed by a first descriptor pointer, and may move an input word from a location in the memory addressed by a source payload pointer to a location in the memory addressed by a destination payload pointer. The pattern matching circuit may perform a pattern matching operation based on the input word and one or more register values. The first descriptor pointer may be modified based on the results of the pattern matching circuit and may generate a second descriptor pointer value.

Device and methods for functional descriptor-based DMA controller

Logic circuits of a digital device may be biased to operate over specific external clock frequency ranges by programming a desired clock oscillator frequency range into a configuration memory of the digital device. In addition, clock source selection may also be programmed into the configuration register. Bias circuits are then configured so that the internal logic of the digital device will operate over the desired clock oscillator frequency range. Non-volatile memory may be used to store the contents of the configuration memory so as to retain the configuration during power down of the digital device. The non-volatile memory may be programmable fuse links, electrically erasable and programmable memory (EEPROM), FLASH memory, etc.

Power optimization when using external clock sources

A mixed signal device having an analog-to-digital converter (ADC) with offset and gain calibration using internal voltage references whereby the digital processor calibrates out offset and gain errors in the analog-to-digital converter by adjusting the analog input amplifier gain and offset or with software compensating the digital representations of the voltages measured. Two different known voltage values are used in determining the offset and gain adjustments needed to calibrate the ADC against the two know voltage values. The mixed signal device may further comprise a Bandgap voltage reference having an accurate known voltage value. Wherein the Bandgap voltage reference may be used for further offset and gain calibration of the ADC to produce substantially absolute voltage values.

Analog-to-digital converter offset and gain calibration using internal voltage references

A high voltage data latch with complementary outputs that are each set to one of two voltage levels (V.sub.pp and V.sub.b). The high voltage data latch is designed using CMOS technology wherein no PMOS transistors have a voltage level greater than V.sub.pp /2 volts across any node. This will allow PMOS transistors with lower voltage breakdown levels to be used. The high voltage data latch has two modes of operation. In a low voltage mode (V.sub.pp =V.sub.DD and V.sub.b =Ground) the outputs switch with respect to the inputs. In a high voltage mode (V.sub.pp &gt;V.sub.b &gt;V.sub.dd) the outputs will be latched to the state they were in when the voltage rails changed states from the low voltage mode to the high voltage mode.

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Pepperell, MA, United States of America

Tim Phoenix