Altera Corporation

Intel Corporation

Tim Michael Vanderhoek

David Lewis

Michael David Hutton

Vaughn Betz

Bruce B Pedersen

Andy Louie Lee

Christopher F Lane

Sinan Kaptanoglu

Srinivas Perisetty

David Cashman

Thomas Yau-Tsun Wong

Sarathy Sribhashyam

Martin Langhammer

Deshanand Pratap Singh

Valavan Manohararajah

Stephen D Brown

Terry Borer

Trevis Chandler

David Galloway

Chris Wysocki

Michael Chan

Ivan Hamer

Przemek Guzy

Steven Caranci

Alexander Grbic

Adrian Ludwin

Lyndon Francis Carvalho

Sadegh Yazdanshenas

Jeffery Christopher Chromczak

Jimmy Kuo

Rebecca Katzin

Zvonko Vranesic

An integrated circuit includes a logic block configured to perform multiplication operations. The logic block includes a plurality of lookup tables configured to receive a plurality of inputs and generate a first plurality of outputs. Additionally, the logic block includes adding circuitry configured to receive the first plurality of outputs and generate a second plurality of outputs. Furthermore, the logic block includes circuitry configured to receive a portion of the plurality of inputs, determine one or more partial products, and generate a third plurality of outputs.

Efficient logic blocks architectures for dense mapping of multipliers

The present disclosure relates generally to techniques for enhancing adders implemented on an integrated circuit. In particular, arithmetic performed by an adder implemented to receive operands having a first precision may be restructured so that a set of sub-adders may perform the arithmetic on a respective segment of the operands. More specifically, the adder may be restructured so that a sub-adder of the set of sub-adders may concurrently output a generate signal and a propagate signal, which may both be routed to a prefix network. The prefix network may determine respective carry bit(s), which may carry into and/or select a sum at a subsequent sub-adder of the restructured adder. As a result, the integrated circuit may benefit from increased efficiencies, reduced latency, and reduced resource consumption (e.g., area and/or power) involved with implementing addition, which may improve operations such as encryption or machine learning on the integrated circuit.

High performance FPGA addition

One embodiment relates to a circuit for pipelined direct-drive routing, the circuit including a routing multiplexer, a flip-flop, and a mode multiplexer. The output of the routing multiplexer is coupled to an input of the mode multiplexer and to the flip-flop. The output of the flip-flop is connected to another input of the mode multiplexer. The flip-flop may be directly connected to the routing multiplexer and the mode multiplexer, or, in an alternate embodiment, the flip-flop may be a member of a pipeline register pool. Another embodiment relates to a circuit for pipelined direct-drive routing which uses a pulse latch. Other embodiments relate to method for pipelined direct-drive routing which includes a degree of logical separation between logic elements and flip-flop elements. Another embodiment relates to a logic array block. Other embodiments, aspects, and features are also disclosed.

Pipelined direct drive routing fabric

A programmable logic device (PLD) includes a non-volatile memory, a configuration memory, and a control circuitry. The control circuitry couples to the non-volatile memory and to the configuration memory. A set of voltages are derived from the outputs of the control circuitry, and are applied to circuitry within the PLD.

Apparatus and methods for power management in integrated circuits

A method for designing a system on a target device includes performing delay annotation where a first delay associated with a first aspect of the system is determined by a first software thread and a second delay associated with a second aspect of the system is determined by a second software thread and the first and second software threads operate in parallel. Ensuring independence between each aspect of the system will facilitate efficient parallelism (i.e. minimal synchronization) while still maintaining serial equivalency.

Method and apparatus for performing delay annotation

A programmable logic device includes an array of functional blocks and input/output elements disposed at the periphery of the programmable logic device. The programmable logic device also includes conductors configured to conduct signals between the functional blocks and between the functional blocks and the routing channels. The number of conductors that propagate signals in a direction toward the periphery and out of the array is greater than the number of conductors that propagate signals into the array in a direction away from the periphery.

Asymmetric signal routing in a programmable logic device

A programmable logic device ('PLD') architecture includes logic elements ('LEs') grouped together in clusters called logic array blocks (LABs&#x201d;). To save area, local feedback resources (for feeding outputs of the LEs in a LAB back to inputs of LEs in the LAB) are reduced or eliminated as compared to in the prior art. Because all (or at least more) of any LE-output-to-LE-input connections of LEs that are working together in a LAB must be routed through the general-purpose input routing resources of the LAB, it is important to conserve those resources. This is accomplished, for example, by giving greater importance to finding logic functions that have common inputs when deciding what logic functions to implement together in a LAB.

Programmable logic device architectures and methods for implementing logic in those architectures

Circuits, methods, and apparatus for including interconnect parasitics without greatly increasing circuit simulation complexity and run times. Interconnect paths are reduced to one of a number of simplified topologies based on path width, length, or other parameters. The input drive waveform is similarly approximated. A grid array is formed in advance, where each point in the grid array corresponds to a set of values relating to a path topology, input waveform, and resulting output waveform. The simplified interconnect path and input waveform are mapped into a set of parameters which corresponds to a location in the predetermined grid array. The output waveform is determined by interpolating output waveforms from gridpoints surrounding the location.

Caching technique for electrical simulation of VLSI interconnect

A programmable logic element grouping for use in multiple instances on a programmable logic device includes more than the traditional number of logic elements sharing secondary signal (e.g., clock, clock enable, clear, etc.) selection circuitry. The logic elements in such a grouping are divided into at least two subgroups. Programmable interconnection circuitry is provided for selectively applying signals from outside the grouping and signals fed back from the logic elements in the grouping to primary inputs of the logic elements in the grouping. The programmable interconnection circuitry limits possible application of at least some of these signals to one or the other of the subgroups, and/or provides for possible application of at least some of these signals to a greater percentage of the primary inputs to one of the subgroups than to the other.

Organizations of logic modules in programmable logic devices

A method for positioning components of a system onto a target device utilizing programmable logic devices (PLDs) is disclosed. A first location on the target device for a first logic region having a first component is determined. Determined properties of the first logic region are preserved. The first logic region is integrated with a second logic region having a second component in view of the determined properties.

Method and apparatus for designing systems using logic regions

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Toronto, Canada

Tim Michael Vanderhoek