Raytheon Company

Hughes Aircraft Company

Tim M Ng

Lloyd Frederick Linder

John M Burns

Kelvin T Tran

Khanh Lam

Kam Wah Kong

Carrie C Lo

A low-noise, low-distortion clamping scheme includes a bootstrapped voltage clamp and an R.sub.gm current clamp that provide superior overdrive protection when used together in a Class-AB feedback amplifier. The bootstrapped voltage clamp includes a transistor that is connected to a circuit node to be clamped. The transistor's base is bootstrapped to the node to maintain a constant V.sub.be when not clamping, to reduce the adverse effects of the junction capacitance C.sub.je which would normally vary with the node voltage and distort the signal at the node. Two such clamps provide positive and negative voltage limiting. The R.sub.gm current clamp is used in the input stage of a Class-AB feedback amplifier to limit the current through the resistor R.sub.gm that interconnects the current inputs of two transconductance amplifiers whenever the voltage drop across R.sub.gm increases to an unacceptable level. The clamp uses a dependent current source whose output current increases with the magnitude of the current flowing through R.sub.gm and prevents that current from exceeding a predetermined limit. When not clamping, the clamp has a very small effect on the amplifier's input stage. Two R.sub.gm current clamps are typically used to limit current flowing in either direction through R.sub.gm.

Overdrive protection clamp scheme for feedback amplifiers

A multiplying digital-to-analog converter for multiplying a bipolar input current by a digital word A having N bits a.sub.i including a current adder for adding a constant current to the bipolar input current to produce a unipolar current, a first current mirror responsive to the unipolar current for providing N binary weighted versions of the unipolar current, a second current mirror for providing binary weighted versions of the constant current, N current selection circuits respectively controlled the N bits a.sub.i for providing an output current comprising (a) the correspondingly weighted version of said unipolar current if the associated control bit is in a first state or (b) the correspondingly weighted version of the constant current if the associated control bit is in a second state, and a shifting circuit for summing the outputs of said N current selection means and for shifting the sum current to produce a bipolar output current representative of product of (a) the input bipolar current and (b) the digital word A.

Two quadrants high speed multiplying DAC

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Monterey Park, CA, United States of America

Tim M Ng