Mitsubishi Semiconductor America, Inc.

Mitsubishi Electric and Electronics U.s.a., Inc.

Tim Lao

Stephen Michael Camacho

Rhonda Cassada

Robert M Walker

Dennis R Blankenship

William L Randolph

A column access system is provided with a column counter for producing a column address in response to an external address. The column address is latched in an address decoder which decodes the column address to select a column in the DRAM. A command decoder generates a column decode enable signal supplied to the address decoder to control latching of the column address, and a write enable signal, together with data, supplied to a write driver. A data latch is provided in the write driver for latching data until an equalize control signal is activated. The latched data signal drives global input/output pair to provide data writing to the DRAM.

System and method for column access in random access memories

One embodiment of an apparatus for generating a boosted voltage to drive a data signal comprises a voltage pump that includes a driver coupled to an input signal for generating the boosted voltage signal from the input signal; a capacitor coupled to the data signal that stores a charge thereof; and an output transistor that delivers an incremental charge to the driver when the drive signal is asserted. Thus, the boosted voltage signal compensates for a change in logic level of the drive signal. In another embodiment, the apparatus also has gates for combining a plurality of data signals into a single disable-on-low signal. The disable-on-low signal is coupled to the output transistor. When all the data signals are at a low logic level, the disable-on-low signal turns off the output transistor, disabling the circuit. As a result, the circuit conserves power by generating the boosted voltage signal only when needed.

Voltage pump for integrated circuit and operating method thereof

A multi-port memory chip is provided with a DRAM main memory and a SRAM cache memory coupled via a global bus. Two clock pins are arranged on the opposite sides of the chip to supply external clock signals. Input clock buffers are provided near pads associated with the clock pins to produce buffered clock signals. A clock generator arranged on the chip uses the buffered clock signals to generate an internal clock signal for synchronizing memory operations. Four local clock buffers distributed on the memory chip are supplied with the buffered clock signals to produce local clock signals for synchronizing data output from data pins.

Dual clocking scheme in a multi-port RAM

An apparatus for driving a bitline driver of a memory array is disclosed. The memory array has row lines, complementary pairs of bitlines driven by bitline drivers, and memory cells at the intersections of the bitlines and the row lines. First and second complementary write data lines provide a bit to be written to the driver and a complement of the bit. A source of a boosted voltage is coupled to a level shifter that conducts the boosted voltage to the bitline driver when the write enable line and the first write data line are asserted. The data bit is latched through a bistable latch to the bitline driver when the write enable line is asserted. A method of driving a bitline of a memory array involves receiving a data bit to be written to the bitline and a complement of the data bit; boosting one of the data bits to a voltage of a magnitude greater than a supply voltage of the memory array; and driving the data bit to a bitline driver.

Driving memory bitlines using boosted voltage

An output buffer is provided to output data read out from a memory array. The output buffer is composed of a main amplifier and an output driver. An input latch stage of the main amplifier is connected to an output of a preamplifier that reads out data from the memory array. A level shifter is coupled to the input latch stage to drive one of transistors in a transistor pair of the output driver. A driver stage is coupled to the input latch stage to drive another transistor in the output driver transistor pair. An output enable signal is supplied to the level shifter and to the driver stage to control the output driver. When the output enable signal is set to a first logic level, the output driver supplies valid data to an external device. When the output enable signal is at a second logic level, the output of the output driver is brought to a floating high-impedance state to disable data output.

High-speed main amplifier with reduced access and output disable time

The power consumed by repetitive switching and precharging of a DRAM bus during repetitive write cycles is reduced by latching the data lines to the DRAM array during repeated data writes in a way which avoids the necessity of precharging the lines before every write. A fast write mode is invoked when repeated writes are to occur and is cleared at the end of the repeated writes.

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San Jose, CA, United States of America

Tim Lao