Intel Corporation

Tim Lambert

Douglas A Guddat

Glenn F King

Peter J DesRosier

Navin Saxena

A processor includes a plurality of I/O connectors and an embedded memory array having a plurality of memory cells and a plurality of bitlines coupled to the plurality of memory cells. The processor also includes low yield analysis circuitry, coupled to both the embedded memory array and a first connector of the plurality of I/O connectors, to provide a coupling between a portion of the embedded memory array and the first connector.

Low yield analysis of embedded memory

A method and apparatus for software controlled timing of embedded memory includes an embedded memory array and input/output (I/O) control circuitry coupled to the embedded memory array. The I/O control circuitry provides a plurality of I/O signals to the embedded memory array to control the input of data to the embedded memory array and output of data from the embedded memory array. The I/O control circuitry also includes programmable delay circuitry to alter the timing of the I/O signals.

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Aloha, OR, United States of America

Tim Lambert