Micron Technology Incorporated

Semiconductor Components Industries, LLC

Aptina Imaging Corporation

Em Microelectronic-marin Sa

Tim J Bales

Sion C Quinlan

Johannes Solhusvik

Serge Bitz

Imaging systems may be provided with stacked-chip image sensors. A stacked-chip image sensor may include a vertical chip stack that includes an array of image pixels, analog control circuitry and storage and processing circuitry. The array of image pixels, the analog control circuitry, and the storage and processing circuitry may be formed on separate, stacked semiconductor substrates or may be formed in a vertical stack on a common semiconductor substrate. The image pixel array may be coupled to the control circuitry using vertical metal interconnects. The control circuitry may route pixel control signals and readout image data signals over the vertical metal interconnects. The control circuitry may provide digital image data to the storage and processing circuitry over additional vertical conductive interconnects coupled between the control circuitry and the storage and processing circuitry. The storage and processing circuitry may be configured to store and/or process the digital image data.

Stacked-chip imaging systems

A system and method to correct or cancel MOS linear region impedance curvature employing an analog solution to trim out the MOS linear region impedance curvature while accommodating PVT spreads in values of internal or external precision resistors. The linear region curvature correction may be obtained by using two MOS transistors in the pad driver/buffer and operating the transistors so as to proportionately increase output impedance of one of them when the output impedance of the other decreases, and vice versa. A linear pad impedance may be maintained over a range of Vpad values, while also maintaining the Vgs supplied to pad driver transistors at its maximum possible value to obtain greater linearity. The approach of the present disclosure relaxes the requirements on the voltage/current references used in the MOS pad drivers and makes tight impedance control possible, especially in a situation where the MOS fabrication process (typically all currently used processes) does not have available an internal precision resistor with a reasonably well controlled value.

MOS linear region impedance curvature correction

A semiconductor package assembly and method for electrically isolating modules, having a capacitor within the semiconductor package assembly. The package assembly and method are suitable for electrically isolating modules according to IEEE 1394.

Semiconductor package assembly and method for electrically isolating modules

An apparatus and associated method are provided for combining a dynamic logic gate and level shifting circuitry in an improved circuit. The combined dynamic logic gate and level shifting circuit of the invention includes a pair of logic gates each having an output and configured such that only one output of the pair is applied at a time to a respective one of a pair of output switching circuits coupled to receive the outputs of the logic gates, wherein a pair of inputs which transition in a first voltage range control the logic gates to produce an output which transitions in a second voltage range in response to the switching of the output switching circuits.

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Bracknell, United Kingdom

Tim J Bales