Micron Technology Incorporated

Tim H Bossart

Pary Baluswamy

David A Kewley

William R Brown

Nikolay A Mirin

Brian R Watson

Jenna L Russon

Scott Jeffrey DeBoer

Ceredig Roberts

Yuan He

Scott L Light

A semiconductor device including conductive lines is disclosed. First conductive lines each comprise a first portion, a second portion, and an enlarged portion, the enlarged portion connecting the first portion and the second portion of the first conductive line. The semiconductor device includes second conductive lines, at least some of the second conductive lines disposed between a pair of the first conductive lines, each second conductive line including a larger cross-sectional area at an end portion of the second conductive line than at other portions thereof. The semiconductor device includes a pad on each of the first conductive lines and the second conductive lines, wherein the pad on each of the second conductive lines is on the end portion thereof and the pad on each of the first conductive lines is on the enlarged portion thereof.

Methods of forming semiconductor devices

Semiconductor devices including conductive lines and methods of forming the semiconductor devices

A semiconductor device including conductive lines is disclosed. First conductive lines each comprise a first portion, a second portion, and an enlarged portion, the enlarged portion connecting the first portion and the second portion of the first conductive line. The semiconductor device includes second conductive lines, at least some of the second conductive lines disposed between a pair of the first conductive lines, each second conductive line including a larger cross-sectional area at an end portion of the second conductive line than at other portions thereof. The semiconductor device includes a pad on each of the first conductive lines and the second conductive lines, wherein the pad on each of the second conductive lines is on the end portion thereof and the pad on the each of the first conductive lines is on the enlarged portion thereof.

Some embodiments include methods for correcting for variation across substrates. A difference map is created to indicate differences between a desired pattern that is to be formed across the substrates utilizing photolithographic processing and a signature pattern representing the actual pattern formed with an initial setting of illumination optics. Modifications to the illumination optics are determined for improving problematic regions identified in the difference map, and the illumination optics are then modified. Substrates are photolithographically processed utilizing the modified illumination optics.

Methods of correcting for variation across substrates during photolithography

The present invention includes a residue-free overlay target, as well as a method of forming a residue-residue free overlay target. The residue-free overlay target of the present invention is defined by trenches or pads including a series of raised lines. The raised lines included in the overlay target of the present invention substantially eliminate any surface topography, such as depressions, at the top surface of overlying material layers, and, thereby, prevent accumulation of process residue which may obscure the overlay target and inhibit further processing. The method of the present invention may be accomplished and modified using process technology known in the semiconductor fabrication art and includes providing a semiconductor substrate, depositing a resist layer, patterning the resist, and executing a wet or dry etch to create at least one overlay target according to the present invention.

Residue free overlay target

The present invention includes a residue-free overlay target, as well as a method of forming a residue-free overlay target. The residue-free overlay target of the present invention is defined by trenches or pads including a series of raised lines. The raised lines included in the overlay target of the present invention substantially eliminate any surface topography, such as depressions, at the top surface of overlying material layers and, thereby, prevent accumulation of process residue which may obscure the overlay target and inhibit further processing. The method of the present invention may be accomplished and modified using process technology known in the semiconductor fabrication art and includes providing a semiconductor substrate, depositing a resist layer, patterning the resist, and executing a wet or dry etch to create at least one overlay target according to the present invention.

Raised-lines overlay semiconductor targets and method of making the same

In the manufacture of a multi-layer integrated circuit, a reference target is etched into a test wafer along with circuit features of a reference layer. As successive dependent layers are printed, successive dependent targets overlaying the same reference target are formed in photoresist. As each successive dependent target is printed, the degree to which it is registered with the reference target is used to determine the overlay error. After determination of overlay error for a layer, the layer's dependent target is removed, allowing the reference target to be matched with the dependent target of another layer.

Layout for measurement of overlay error

In the manufacture of a multi-lay integrated circuit, a reference target is etched into a test wafer along with circuit features of a reference layer. As successive dependent layers are printed, successive dependent targets overlaying the same reference target are formed in photoresist. As each successive dependent target is printed, the degree to which it is registered with the reference target is used to determine the overlay error. After determination of overlay error for a layer, the layer's dependent target is removed, allowing the reference target to be matched with the dependent target of another layer.

Disclosed is a spin coating apparatus and method for coating a semiconductor wafer of known diameter with a thin and substantially uniform coating of a solution. The apparatus comprises a containment bowl with a rotatable vacuum chuck, having a diameter less than hat of the wafer, rotatably mounted inside the bowl. The vacuum chuck captively holds a bottom surface of the wafer. Directly beneath the bottom surface of the wafer is a substantially frustroconical deflector ring. The deflector ring is concentrically attached about and stationary with respect to the rotatable vacuum chuck. The top surface of the ring is located just below and in close-spaced parallel relation to the bottom surface of the wafer. The top face of the deflector has a minimum diameter that is greater that the diameter of the semiconductor wafer. With the system of this invention the requirement of an organic solvent wash of the wafer backside after the coating of the wafer top surface is eliminated.

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Boise, ID, United States of America

Tim H Bossart