Apple Inc.

Harris Corporation

Nellcor Incorporated

Tim G Godfrey

John R Nelson

Wayne K Wong

Gregory J Pettit

A technique for operating a wireless communication device includes transmitting a first downlink rate in a first control message. The first downlink rate is based on a latency of an inter-processor communication link associated with the wireless communication device. First downlink data at the first downlink rate is then received for a first time period. Following the first time period, second downlink data is received at a second downlink rate that is higher than the first downlink rate.

Techniques for reducing buffer overflow in a communication system

To prevent entry of contaminants into a craft unit, each of a telephone signal connector (RJ11 jack) and DIN-type digital signalling link connector is replaced with a sealed, multi-pin plug/receptacle type connector which integrates the routing of both telephone communication signals and digital communication signals between the craft unit and an external device. When stored in a storage and battery-charging station, the craft unit is maintained in a communication-ready state, by providing each of the battery-charging holder and the portable craft unit with an additional multi-pin interconnect arrangement, that contains a charging path for the craft unit's internal battery, and a multi-pin signalling path. This multi-pin interconnect arrangement contains both a set of communication signalling pins and a set of terminal pins through which the internal battery of the portable craft unit is charged. Within a receiving cup-like portion of the storage and battery charging unit, a plurality of male connector pins are nested in a compact linear arrangement to engage a corresponding set of female connector terminals supported within the portable craft unit.

Battery charging and signalling interconnect arrangement for craftsperson's

A graphics coprocessor adapter with hardware support for horizontal scrolling is disclosed. A graphics processor provides both a row address with a RAS signal and a column address with a CAS signal to two banks of video RAMs. Both banks are provided with the same scrolling column address signal. Translating logic intercepts the column address signal for the static plane RAM bank and translates it into a fixed value. Thus, a single column address signal can control both the scrolling and static planes.

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Overland Park, KS, United States of America

Tim G Godfrey