Micron Technology Incorporated

Tim G Damon

Phillip E Byrd

David D Siek

Blane Holden

Mike Pearson

Dan Dean

Matt Adsitt

A CAM device that performs operations on-chip during testing. The CAM device can, for example, include circuitry that compares search results with an expected address to determine whether the expected address is defective. The CAM can be tested by applying search data and the expected address to the CAM at the same time, and determining if a match occurs at the expected address. In another approach, a reset match enable is used to limit the search to only a CAM memory location that has been written to, thereby limiting the test search to only the location containing test data.

CAM expected address search testmode

A voltage is applied across a control resistor, and the voltage is caused to decay. The decay is monitored by a testing circuit such as a comparator. When the voltage across the control resistor has decayed to a value less than or equal to a reference voltage in the comparator, a switch time period is established. Fuses in a memory device are tested against the established switch time period. The fuses are tested in a similar fashion: a voltage is applied across the fuse being tested, and the voltage is caused to decay. The comparator monitors the decay of the voltage across the fuse. If the resistance value of a fuse being tested is within specification, the comparator changes its state at a time equal to or less than the switch time period established for the control resistor. Testing time for fuses can further be minimized by having an external access to the reference in the comparator. In establishing the switch time period by applying a voltage across the control resistor, the voltage of the reference in the comparator is adjusted to establish quicker switch time periods against which fuses are tested. In this manner, testing time is minimized.

Apparatus and method for testing fuses

A method of testing and/or repairing a memory device having two arrays of memory cells arranged in rows and columns. Sense amplifiers shared by the arrays are selectively coupled by isolation transistors to the digit lines of respective columns in each array. The sense amplifiers and isolation transistors are controlled to sequentially writing known data bits to a plurality of rows in each of the arrays. The rows in the first and second arrays remain activated for a testing interval of sufficient duration to allow charge to transfer through any inter-cell defects between the cells in the activated rows and cells that are not in an activated row. Cells in each non-activated row are then read. Inter-cell defects may also be repaired by activating the rows in the first and second arrays in a manner that couples adjacent memory cells to digit lines having different complimentary voltages.

Method for detecting or repairing intercell defects in more than one array of a memory device

A system is disclosed for evaluating relevant data across independent test sequences and providing a consumable output to give a tester an accurate account of the test data. A method for reporting the results of the test processes includes several steps. First, repair, trending, characterization, timing and engineering data for two separate test sequences are read. Next, the data is compared. Also, an analytical report of the test data comparisons is assembled and output.

System for evaluating and reporting semiconductor test processes

A method of testing a memory device having two arrays of memory cells arranged in rows and columns. Sense amplifiers for respective columns are shared by the arrays, with the sense amplifiers being selectively coupled to the digit lines of respective columns in each array by respective isolation transistors. Cells of the memory array are tested by first writing known data bits to each of the cells. The isolation transistors for the first array are then turned on, and the isolation transistors for the second array are turned off. Predetermined voltages are coupled to the sense amplifiers through the digit lines of the first array by activating a row in the first array. A plurality of rows in the first array are then activated to couple the memory cells in each activated row to respective digit lines. The sense amplifiers are then coupled to respective digit lines in the second array by turning on the isolation transistors for the second array. A plurality of rows in the second array are then activated to couple the memory cells in each activated row to respective digit lines of the second array. The rows in the first and second arrays remain activated for a testing interval of sufficient duration to allow charge to transfer through any inter-cell defects between the cells in the activated rows and cells that are not in an activated row. The cells that are not in an activated row are then read to determine if the data originally written to the cells was altered by charge flowing through inter-cell defects. Inter-cell defects may also be repaired by activating the rows in the first and second arrays in a manner that couples adjacent memory cells to digit lines having different complimentary voltages.

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Bosie, ID, United States of America

Tim G Damon