Intel Corporation

Tim Foley

Rahul P Sathe

Karthik Vaidyanathan

Robert M Toth

Various embodiments provide for a new texture address mode that excludes any texture filter taps (i.e. coordinates) that fall outside the texture domain from the filtering process. Taps outside a texture domain are not considered in one embodiment. Also, various embodiments provide flexibility as to the texture coordinate locations tand values of weights w. The tap weight can be modified as a function of tap location and in particular whether a tap is within a texture.

Texture address mode discarding filter taps

An apparatus may include an index buffer to store an index stream having a multiplicity of index entries corresponding to vertices of a mesh and a vertex cache to store a multiplicity of processed vertices of the mesh. The apparatus may further include a processor circuit, and a vertex manager for execution on the processor circuit to read a reference bitstream comprising a multiplicity of bitstream entries, each bitstream entry corresponding to an index entry of the index stream, and to remove a processed vertex from the vertex cache when a value of the reference bitstream entry corresponding to the processed vertex is equal to a defined value.

Techniques and architecture for improved vertex processing

In accordance with some embodiments, domain shader and/or tessellator operations can be eliminated when they are redundant. By using a corner cache, a check can determine whether a given corner, be it a vertex or a quadrilateral corner, has already been evaluated in the domain shader and/or tessellator and if so, the result of the previous operation can be reused instead of performing unnecessary invocations that may increase power consumption or reduce speed.

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Concord, CA, United States of America

Tim Foley