Cypress Semiconductor Corporation

Tim Fiscus

Dave Eugene Chapman

Chris Smith

David G Chapman

A timer circuit is disclosed. The timer, having a delay configured to track inversely with temperature of the memory device, includes a reference signal configured to increase in voltage, as the temperature of the memory device increases. The reference signal may be generated from a current that is derived from a bandgap reference circuit. The timer circuit includes a pull-down path made up of a plurality of selectable pull down transistors which are coupled to the reference signal at the gate. Resistance of the pull-down path is reduced as the reference signal is increased and the reduced resistance of the pull-down path decreases the delay of timer. A plurality of selectable delay elements may be preconfigured to adjust the delay and are coupled to the output path of the current starved inverter.

Delay inversely proportional to temperature timer circuit

A power supply detecting input receiver circuit () can include a multiplexing capability that can select one of at least two power supplies during a non-critical timing period. Such selection of a power supply can reduce both the standby and the active current of input receiver circuit (). In one arrangement, an input receiver circuit () can include a comparator (), a latch (), and a select circuit (). A latch () can be enabled to indicate a selection of a supply upon a circuit power-up, as but one example. A method is disclosed that includes comparing at least two supply voltages, setting a latch to indicate a selected supply, and providing the selected supply to an input receiver. The receiver output signal may be voltage-translated to a suitable internal supply level.

Power supply detecting input receiver circuit and method

A method of performing memory operations of a memory device having precharge, read and write states is disclosed. The method includes refreshing the memory device provided a refresh timer expired and the memory device is in the precharge state. The method further includes entering the precharge state, refreshing the memory device and returning to the read state provided the memory device is in the read state for a predetermined period of time. The memory device is refreshed provided the memory device is transitioning from the read state to the write state and the refresh timer has expired.

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South Burlington, VT, United States of America

Tim Fiscus