Altera Corporation

Altera Corporaton

Tim Allen

Jeffrey Orion Pritchard

Michael Fairman

Bryan H Hoyer

James M Brown

Mike Fairman

Kerry S Veenstra

Andy Louie Lee

Keith Duwel

Aaron Ferrucci

Chris Lane

Mario E Guzman

Chris Adler

A system for designing a circuit, which includes a module, uses a computer. A user may program or adapt the computer to perform computer-aided design functions. The computer obtains a description of the module from the user. The computer parses the description of the module to identify a port of the module, and to obtain information about the port. The computer presents to the user the information that it has obtained about the port.

Apparatus and methods for importing hardware design and generating circuit interfaces

Methods and apparatus are provided for implementing parameterizable processor cores and peripherals on a programmable chip. An input interface such as a wizard allows selection and parameterization of processor cores, peripherals, as well as other modules. The logic description for implementing the modules on a programmable chip can be dynamically generated, allowing extensive parameterization of various modules. Dynamic generation also allows the delivery of device driver logic onto a programmable chip. The logic description can include information for configuring a dynamically generated bus module to allow connectivity between the modules as well as connectivity with other on-chip and off-chip components. The logic description, possibly comprising HDL files, can then be automatically synthesized and provided to tools for downloading the logic description onto a programmable chip.

Methods and apparatus for implementing parameterizable processors and peripherals

Methods and apparatus are provided for providing a first master component with access to a first slave component while a second master component is accessing a second slave component in a system. The system may include a processor core and peripherals implemented on an integrated circuit. A slave side arbitrator corresponding to a single slave component and coupled to multiple master components can be used to provide a master component access to a slave component.

Master and slave side arbitrators associated with programmable chip system components

A programmable logic device (PLD) is provided. The PLD includes a microprocessing unit (MPU) and a memory region functioning in a read only state. A Joint Test Action Group (JTAG) debug module in communication with the memory region is included in the PLD. The JTAG debug module is able to detect a breakpoint causing an interruption of a processing sequence executed by the MPU. Write control circuitry capable of issuing a signal enabling the memory region to transition from the read only state disallowing writes to a second state accepting write data from the MPU is included in the JTAG debug circuitry. In one embodiment, the write control circuitry issues the signal in response to a breakpoint induced either through hardware or software. A method of debugging a PLD is also provided.

Method and apparatus for debugging embedded systems having read only memory

A programmable logic system includes a reconfigurable programmable logic device and configuration storage that stores at least two configurations. A default configuration loads first and then loads the desired user application configuration. If the user application configuration fails, the system saves data regarding the failure and then returns to the default configuration for recovery. The default configuration, after reading the failure data, causes an operator to be called to intervene, or loads a different (e.g., previous) configuration if one is available in configuration storage. The system is particularly useful where the user can update configurations remotely. In an alternative mode, the system stores only the user configuration (which is loaded first) and the default configuration. If a newly-loaded configuration fails, the default configuration is loaded and signals the operator or takes other action short of loading a different configuration.

Reconfigurable programmable logic system with configuration recovery mode

Methods and apparatus are provided for efficiently implementing a programmable chip using hardware description source files passed through multiple tools. A hardware description language source file is provided with mechanisms to allow tool-specific code to be handled by both a synthesis tool and by a simulation tool. Instructions are provided to direct a synthesis tool to read as code comments that a simulation tool is configured to disregard.

Methods and apparatus for selective comment assertion

Methods and apparatus are provided for configuring and generating a sequence of discrete output signal values. A microcontroller writes output signal values to memory and provides address and timing information to a streaming output peripheral. The streaming output peripheral uses the address and timing information to read output signals values from memory and provide the output signal values in a clock cycle accurate manner.

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Santa Cruz, CA, United States of America

Tim Allen