Motorola Corporation

Tim A Williams

Nicholas R Van Bavel

Wendell L Little

Eric F Ziolko

Luis A Bonet

Jose G Corleto

David L Weiss

Shawn R McCaslin

A data processor having a split level control store structure, which partitions program memory into a macrocode portion and a microcode portion. The data processor contains two distinct machines, a macromachine and a micromachine. The macromachine includes an instruction sequence controller which detects the macrocode branch instruction before it is perceived by the micromachine, extracts from the branch instruction a macroaddress, and then provides the extracted macroaddress to the program memory as the next sequential instruction address. By 'pipelining' the macromachine, the macromachine can 'execute' the branch instruction in parallel with, and independent of, the execution by the micromachine of the preceeding instruction.

Data processor having split level control store

A data processing system uses the same structure and hardware to implement either a general purpose multiplier or arithmetic operations associated with the least-mean-squares (LMS) algorithm. Multiplier and adder circuits are time-shared to perform the myriad functions. In one form, further modified Booth's algorithm is utilized so that an output product of two binary input numbers may be quickly formed by executing a series of multiplications and accumulations. The operation is pipelined for continuous processing activity.

Data processor with combined adaptive LMS and general multiplication

A digital tone detector receives a modulated input signal selectively containing at least one tone signal component. Two demodulator circuits each demodulate the input signal wherein one demodulator circuit operates at the predetermined frequency of the tone and the other demodulator circuit operates at the second harmonic. When the input tone has a low spectral harmonic power, a ratio of the demodulated outputs of the two demodulators reliably detects the presence of the tone in the input signal.

Digital tone detector using a ratio of two demodulators of differing

A systolic IIR decimation filter for use with an oversampled A/D converter. The filter includes a pole section having coefficients selected to generate complex pole pairs positioned to shape the filter output. A full multiplication of the coefficients is decomposed into an equivalent number of digital shifts and adds in accordance with a modified Booth's algorithm. The filter further includes a zero section for cancelling unwanted pole pairs produced by the decomposition and delays required for systolic operation. At least portions of the pole section are utilized in the zero section during times when redundant information is present in order to reduce equipment and provide decimation.

Systolic IIR decimation filter

An array multiplier utilizing a predetermined recoding algorithm minimizes operating speed by using two different radices. Special product terms must be formed to implement the recording algorithm. In order to avoid delaying the computation of partial products until after the time special products are formed, two recoding radices may be used. Partial products can be calculated from terms formed by a smaller sized radix during the same time the special product terms are being calculated. Initial use of the smaller radix eliminates an immediate need for the special product bits which improves multiplier speed by minimizing time required to form a final product.

Mixed size radix recoded multiplier

A filter processor implements the least mean squares (LMS) algorithm in an N tap digital filter in (N+1) time cycles, where N is an integer. A filter structure is shown which is implemented with a processor having an update portion and a convolution portion. A single memory is shared between the two portions, and the same data is concurrently coupled to both portions for concurrent use. The filter may be efficiently pipelined wherein successive adaptive and convolution operations are executed to efficiently implement an N tap filter with a minimum amount of circuity.

Pipelined processor for implementing the least-mean-squares algorithm

An oversampling converter for converting an analog input signal to a high resolution digital equivalent is provided. The oversampling converter uses sigma delta modulation utilizing single integration. A plurality of quantization circuits provide a plurality of output signals, each output signal containing data information and an error component. Each quantization circuit performs an integration of a difference of an input signal and a feedback signal before quantizing the integrated signal as one of the output signals. A filter, such as a decimation filter, is coupled to the converter for receiving the multiple outputs of the converter and providing a filtered converted digital output signal.

Multiple output oversampling A/D converter with each output containing

An oversampling A/D converter for high resolution data conversion is provided. An analog input signal is quantized into a digital equivalent value with a finite quantization error associated therewith in a first circuit portion. An analog low pass filter is inserted between the first circuit portion and a second circuit portion similar in function and circuitry to the first circuit portion. The second circuit portion functions to remove the error of the first circuit portion from an output signal by providing a signal component, which when added with the output of the first circuit portion cancels the error of the first circuit portion. The low pass filter provides attenuation of quantization error provided by the second circuit portion which results in an output signal with a significantly attenuated error.

Oversampled A/D converter using filtered, cascaded noise shaping

An oversampled A/D converter which utilizes digital error correction is provided. In one form, the present invention is used with a sigma delta modulator having a plurality of rank ordered quantization loops, Each quantization loop contains an analog integrator circuit of predetermined gain which is subject to variation, thereby introducing errors. When the product of a reciprocal of the analog integrator gain and the gain of a digital gain stage of a subsequent quantization loop equals one, minimum noise exists in the data conversion. A digital gain control circuit is coupled to the digital gain stage for adjusting the gain of the digital gain stage during a calibration mode to provide minimum noise in the converter, thereby compensating for errors attributable to the analog integrator circuit.

Oversampled A/D converter having digital error correction

A pipelineable multiplier which implements two's complement Modifiied Booths' algorithm multiplication. Partial product bits are formed to create an array having an integer number of rows and columns. An addition of partial product bits of each row is accomplished in pipelined fashion by using an arithmetic machine for each row. Each arithmetic machine is a time multiplexed summer including a plurality of full adders, the number of full adders being proportional to a ratio of the sum and carry bit propagation delays of each of the full adders. In one form, full adders having a carry propagation delay substantially twice as fast as a sum propagation delay are used in the pipelineable structure.

Pipelineable structure for efficient multiplication and accumulation

A pipelined multiplier which serially receives a signed input multiplicand and a signed multiplier to generate a signed serial output product is provided. The multiplier utilizes a technique which simplifies the addition of partial product bits by creating a uniform partial product array. Columns of partial product bits are sequentially added in a pipelined structure. Carry bits which are generated during the column addition of partial product bits are delayed in the pipeline and coupled back to the input of the pipeline at the appropriate time for another addition of column bits as product bits are serially outputted. By minimizing delays in the pipeline, multiplication of signed operands of large bit length may be quickly performed.

Serial two's complement multiplier

A method which reduces the memory required to store correction factors used in logarithmic addition and subtraction of logarithmic operands. The method is implemented by a circuit which adds a predetermined correction factor to the minimum value of two logarithmic input operands. Correction factors are quantized to single polarity values. Predetermined ranges of magnitude values of the correction factors are selected in which the minimum value of each range is represented by a bias level. As a result of the bias levels, stored representations for the addition and subtraction factors are made much smaller resulting in less memory which is required. An addition of a predetermined bias level to the minimum value is effected simultaneous to addressing a predetermined adjustment factor in the reduced memory. A second addition is required to provide an output which represents either an addition or subtraction of the signed operands.

Method and apparatus for minimizing a memory table for use with

A circuit for receiving a plurality of signed operands which each represent an exponential value to a predetermined base and for selecting one of the operands which results in a maximum value is taught. The circuit has a rank ordered plurality of logic circuits which each receives a predetermined bit of each operand and provides an output bit of the maximum value. The output of the logic circuits is a transcoded output which is a translation value of the maximum value. A sign control circuit receives a sign bit of each signed operand and controls the operation of the logic circuits in response to the values of the input operands.

Circuit for selecting one of a plurality of exponential values to a

In a digital signal processing system, a logarithmic arithmetic logic unit which selectively performs multiply/accumulate operations of operands in logarithmic number representation. Direct feed through of operands through an adder/subtractor circuit, even when an addition or subtraction is not effected, eliminates external bypass circuitry. A method for adding and subtracting operands in logarithmic number representation. An adder/subtractor circuit which efficiently effects addition and subtraction of operands in logarithmic number representation over a wide dynamic range.

Circuit for adding and/or subtracting numbers in logarithmic

A modulo arithmetic unit and method for providing a sum of first and second numbers is provided. In one form, a first adder calculates a first sum which is equal to the arithmetic sum of the first and second numbers. A second adder is provided for adding the first number to an offset value equal to (2.sup.X -M), where X defines the number of bits of the number system used, M is a predetermined modulus and X and M are integers. A third adder operates in parallel with the first adder to calculate the sum of the output value of the second adder and the second operand to provide a second output sum and a carry output bit. In another form, only two adders are utilized wherein the first adder calculates a first output sum of the first and second numbers, and the second adder calculates the sum of the first output sum and the offset value. Both illustrated forms utilize a multiplexer which outputs one of the two calculated output sums depending upon whether a wraparound of an upper modulus boundary occurred.

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Austin, TX, United States of America

Tim A Williams