Intel Corporation

Tiffany J Kasanicky

Wei P Chen

Rajat Agarwal

Chet R Douglas

Andy M Rudoff

Siddhartha Chhabra

Mohan J Kumar

Hormuzd M Khosravi

Murugasamy K Nachimuthu

Mahesh S Natu

Anand K Enamandram

Robert A Branch

Deepak Gandiga Shivakumar

Dan J Williams

Manjula Peddireddy

Krzysztof Rusocki

Nicholas Moulin

Wei Chen

Systems, methods, and apparatuses to implement spatially unique and location independent persistent memory encryption are described. In one embodiment, a system on a chip (SoC) includes at least one persistent range register to indicate a persistent range of memory, an address modifying circuit to check if an address for a memory store request is within the persistent range indicated by the at least one persistent range register, and append a unique identifier value, for a component corresponding to the memory store request for the address, to the address to generate a modified address and output the modified address as an output address when the address is within the persistent range, and output the address as the output address when the address is not within the persistent range, and an encryption engine circuit to generate a ciphertext based on the output address.

Circuitry and methods for spatially unique and location independent persistent memory encryption

Systems, apparatuses and methods may provide for technology that exchanges activation information between system firmware and an operating system (OS), wherein the activation information includes one or more of status information, activation state information, capability information, activation time information or quiesce time information. The technology also conducts a runtime upgrade of the device firmware based on the activation information, wherein the runtime upgrade bypasses a reboot of the computing system.

Interface and warm reset path for memory device firmware upgrades

A memory management system includes a cache invalidation logic configured to invalidate, based a cache invalidation event, cache entries within a cache memory by having each cache entry, of the cache entries within the cache memory, reference a respective dummy address from among dummy addresses within a dummy address space, wherein the cache memory is assigned to a memory, the memory has a memory address space associated therewith to provide access the memory, and each dummy address of the dummy addresses within the dummy address space is distinct from any address of the memory address space.

Memory system, computing system, and methods thereof for cache invalidation with dummy address space

According to various aspects, a memory system may include: a memory having a memory address space associated therewith to access the memory; a cache memory assigned to the memory; one or more processors configured to generate a dummy address space in addition to the memory address space, each address of the dummy address space being distinct from any address of the memory address space, and generate one or more invalid cache entries in the cache memory, the one or more invalid cache entries referencing one or more dummy addresses of the dummy address space.

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Longmont, CO, United States of America

Tiffany J Kasanicky