Intel Corporation

Tieyu Zheng

Raghuram Narayan

Xiaoqing Ma

Sairam Agraharam

Thomas G Ruttan

Tyler N Osborn

Manohar S Konchady

James A Irvine

Robert R Martinson

Sumit Kumar

Sridhar Nara

Renee D Garcia

Suresh B Yeruva

Lynn H Chen

David W Grawrock

Bruce Querbach

Keshavan K Tiruvallur

Mark B Trobough

Chinna B Prudvi

Hermann Gartler

Vui Yong Liew

Ashok N Kabadi

Keith A Drescher

Samie B Samaan

Mukesh Kataria

Jay Joseph Nejedlo

Eric J Zbinden

Lyle E Cool

Russell J Wunderlich

James J Grealish

Brian Meyer

Abhijit Davare

Priyadarsan Patra

William Penner

Ridvan A Sahan

Rahima K Mohammed

Wee Hoo Cheah

Yuen Tat Lee

Arun R Ramadorai

John L Baudrexl

Kapila B Udawatta

Christian E Iovin

Kip C Killpack

Kyle Markley

Loren James McConnell

Yi Amy Xia

Edwin E Parks

Padmakumar Gopal

Sanjay S Salem

Travis K Goff

David C Florey

Evan J Halprin

Jiun Long Foo

Selvakumar Raja Gopal

Neil Dobler

Yupeng Li

Nagib Z Hakim

Mandy G Mistakawi

Timothy S Storey

An apparatus and method is described herein for providing a test, validation, and debug architecture. At a target or base level, hardware hooks (Design for Test or DFx) are designed into and integrated with silicon parts. A controller may provide abstracted access to such hooks, such as through an abstraction layer that abstracts low level details of the hardware DFx. In addition, the abstraction layer through an interface, such as APIs, provides services, routines, and data structures to higher-level software/presentation layers, which are able to collect test data for validation and debug of a unit/platform under test. Moreover, the architecture potentially provides tiered (multiple levels of) secure access to the test architecture. Additionally, physical access to the test architecture for a platform may be simplified through use of a unified, bi-directional test access port, while also potentially allowing remote access to perform remote test and debug of a part/platform under test. In essence, a complete test architecture stack is described herein for test, validation, and debug of electronic parts, devices, and platforms.

Test, validation, and debug architecture

An integrated circuit (IC) package stack with a first and second substrate interconnected by solder further includes solder resist openings (SRO) of mixed lateral dimension are spatially varied across an area of the substrates. In embodiments, SRO dimension is varied between at least two different diameters as a function of an estimated gap between the substrates that is dependent on location within the substrate area. In embodiments where deflection in at least one substrate reduces conformality between the substrates, a varying solder joint height is provided from a fixed volume of solder by reducing the lateral dimensioning of the SRO in regions of larger gap relative to SRO dimensions in regions of smaller gap. In embodiments, the first substrate may be any of an IC chip, package substrate, or interposer while the second substrate may be any of another IC chip, package substrate, interposer, or printed circuit board (PCB).

Integrated circuit package with spatially varied solder resist opening dimension

An embodiment of the present invention is a method of making a Land Grid Array (LGA) socket. A contact area of a socket is divided into a first L-shaped area and a second L-shaped area. The first L-shaped area has a first center, a first outer long side, and a first outer short side. The first L-shaped area contains a first set of contacts oriented in a first direction. The second L-shaped area has a second center, a second outer long side, and a second outer short side and is located symmetrically to the first L-shaped area. The second L-shaped area contains a second set of contacts oriented in a second direction opposite to the first direction such that pressing a device on the first and second sets of contacts results in approximately zero force and moment.

Method of making a self-balanced dual L-shaped socket

An LGA socket assembly comprising individual sockets cells, the methods of fabricating and assembling the socket cells into a socket assembly. In an embodiment of the invention, each socket cell comprises an insulative body and a wire. The insulative body is formed around the wire. A first portion of the wire extends from the top surface of the insulative body to form contact tip. A second portion of the wire extends from the bottom surface of the insulative body to form contact paddle. Socket cells are aligned to form a socket assembly.

Land grid array (LGA) socket with cells and method of fabrication and assembly

An apparatus may include an integrated circuit package comprising a plurality of conductive pads and having a face, and a socket coupled to the integrated circuit package and to the conductive pads, the socket having a footprint. In some aspects, the footprint is smaller than the face.

Extended package substrate

Apparatus including a body as an intermediary between a device and a printed circuit board, the body including a contact area defined by a plurality of openings each to accommodate a contact therethrough and an alignment feature adjacent the contact area and protruding from a plane defined by the contact area, wherein a surface of the alignment feature includes a friction-reducing material. A method including contacting an alignment feature of a socket with a friction-reducing material. Apparatus and system including a body as an intermediary between a device and a printed circuit board; a plurality of contacts each disposed through a contact area of the body and oriented to deflect a device in a first direction; and a load plate coupled to the body and configured to apply an actuation force on a device in a different second direction. A method including inserting a device into a socket.

Lateral force countering load mechanism for LGA sockets

Disclosed is a socket assembly for electrically engaging an Integrated Circuit (IC) package with a printed circuit board. The socket assembly includes a socket body and a Pick-and-Place (PnP) cap. The socket body is mounted on the printed circuit board. Further, the PnP cap is capable of detachably mounting on the socket body. An upper surface of the PnP cap includes a raised portion with multiple chamfered portions projecting out from the raised portion. The multiple chamfered portions enable easier detachment of the PnP cap from the socket body.

Pick-and-place cap for socket assembly

A land grid array socket and a microelectronic assembly including the socket. The socket comprises: a housing; an array of through-contacts on the housing; a solder ball standoff element on a PCB side of the housing; and a seating plane standoff element on a package side of the housing, the seating plane standoff element being aligned with the solder ball standoff element to form a loading force support element therewith.

Socket for land grid array package

In some embodiments, a socket assembly, electronic assembly and electronic system provide current paths for supplying power and I/O signals to a processor. The socket assembly includes a base having an upper surface and a lower surface with a plurality of contacts extending from the upper surface of the base. Each of the contacts is adjacent to another contact such that each of the contacts is part of a differential pair of contacts. Each of the contacts includes a first side and a second side. One of the contacts in each differential pair of contacts is oriented in one direction while the other contact in each differential pair of contacts is oriented in an opposing direction such that the first side of one of the contacts in each differential pair faces in an opposite direction to the first side of the other contacts in each differential pair.

Socket assembly that includes improved contact arrangement

Disclosed is a socket assembly for electrically engaging an IC package with a PCB. The socket assembly includes a socket body, a loading mechanism, and a pick-and-place (PnP) cap. The socket body engages the IC package with the PCB. The loading mechanism includes a loading plate having a central opening and capable of being mounted on the socket body when the loading plate is in a closed position. The PnP cap includes a first plurality of latches configured on a plurality of peripheral edges of the PnP cap and a raised portion configured on an upper surface of the PnP cap. The first plurality of latches engages the PnP cap with the socket body when the PnP cap is in a first position. The second plurality of latches detachably engages the PnP cap with the central opening of the loading plate when the PnP cap is in a second position.

Socket assembly for securing socket body

An embodiment of the present invention is a Land Grid Array (LGA) socket. A first L-shaped area has a first center, a first outer long side, and a first outer short side. The first L-shaped area contains a first set of contacts oriented in a first direction. A second L-shaped area has a second center, a second outer long side, and a second outer short side and is located symmetrically to the first L-shaped area. The second L-shaped area contains a second set of contacts oriented in a second direction opposite to the first direction such that pressing a device on the first and second sets of contacts results in approximately zero force and moment.

Self-balanced dual L-shaped socket

According to a first embodiment of the invention, a Land Grid Array (LGA) socket includes two sets of spring-loaded contacts, the contacts in the first set having an orientation opposite the contacts in the second set. Each set of contacts is positioned such that the total force and total moment of about the socket center by the wiping of the contacts is near zero. According to a second through fourth embodiment of the invention, a rectangular socket may be formed. According to these embodiments, the contacts are divided into four sets. Each set may have a different orientation, arranged so that the total force and moment are near zero.

Self-balanced land grid array socket

A low-profile package for housing an optoelectric device is disclosed. The low-profile package includes an insulating base having an upper surface. The optoelectric device is mounted to the upper surface of the insulating base. The low-profile package also includes a metal sealing member having a top wall and a bottom wall. The bottom wall of the metal sealing member is attached to the upper surface of the insulating base. The low-profile package further includes a substantially flat metal cover attached to the top wall of the metal sealing member to thereby hermetically seal the metal cover to the insulating base.

Low-profile package for housing an optoelectronic assembly

Growing community of inventors

Chandler, AZ, United States of America

Tieyu Zheng