Alpha Omega Semiconductor Inc.

Monolithic Power Systems, Inc.

Chengdu Monolithic Power Systems Co., Ltd.

Chengdu Monolithic Power Systems, Inc.

Tiesheng Li

Anup Bhalla

Hong Chang

Sik Lui

Yu Wang

Sung-Shan Tai

Lei Zhang

Rongyao Ma

Donald Ray Disney

Daniel Ng

Moses Ho

Yingying Lou

John Chen

Yeeheng Lee

Michael Ren Hsing

Ognjen Milic

Il Kwan Lee

Daping Fu

Deming Xiao

Huaifeng Wang

This invention discloses a new switching device supported on a semiconductor that includes a drain disposed on a first surface and a source region disposed near a second surface of said semiconductor opposite the first surface. The switching device further includes an insulated gate electrode disposed on top of the second surface for controlling a source to drain current. The switching device further includes a source electrode interposed into the insulated gate electrode for substantially preventing a coupling of an electrical field between the gate electrode and an epitaxial region underneath the insulated gate electrode. The source electrode further covers and extends over the insulated gate for covering an area on the second surface of the semiconductor to contact the source region. The semiconductor substrate further includes an epitaxial layer disposed above and having a different dopant concentration than the drain region. The insulated gate electrode further includes an insulation layer for insulating the gate electrode from the source electrode wherein the insulation layer having a thickness depending on a Vgsmax rating of the vertical power device.

Power MOSFET device structure for high frequency applications

The present disclosure discloses a field effect transistor ('FET'), a termination structure and associated method for manufacturing. The termination structure for the FET includes a plurality of termination cells arranged substantially in parallel from an inner side toward an outer side of a termination area of the FET. Each of the termination cells comprises a termination trench and a guard ring region located underneath the bottom of the termination trench in the semiconductor layer. Each termination trench is lined with a termination insulation layer, and is filled with a first conductive spacer and a second conductive spacer respectively against an inner sidewall and an outer sidewall of the termination trench and spaced apart from each other with a space, and a dielectric layer filling the space between the first and the second spacers.

Field effect transistor, termination structure and associated method for manufacturing

A semiconductor device having an ESD protection structure and a method for forming the semiconductor device. The ESD protection structure is formed atop a termination area of the substrate and is electrically coupled between a source metal and a gate metal of the semiconductor device. The ESD protection structure has a first portion adjacent to the source metal, a second portion adjacent to the gate metal and a middle portion between and connecting the first portion and the second portion, wherein the middle portion has a first thickness greater than a second thickness of the first portion and the second portion. Such an ESD protection structure is beneficial to the formation of interlayer vias which are formed to couple the ESD protection structure to the source metal and the gate metal.

Semiconductor device and associated method for manufacturing

A field effect transistor ('FET'), a termination structure and associated method for manufacturing. The FET has a plurality of active transistor cells and a termination structure. The termination structure for the FET includes a plurality of termination cells arranged substantially in parallel from an inner side toward an outer side of a termination area of the FET. Each of the termination cells comprises a termination trench lined with a termination insulation layer and filled with a termination conduction layer. The innermost termination cell is electrically coupled to gate regions of the active transistor cells while the rest of the termination cells are electrically floating.

A semiconductor device with a substrate, an epitaxy layer formed on the substrate, a plurality of deep wells formed in the epitaxy layer, a plurality of trench gate MOSFET units each of which is formed in top of the epitaxy layer between two adjacent deep well, wherein a trench gate of the trench gate MOSFET unit is shallower than half of the distance between two adjacent deep wells, which may reduce the product of on-state resistance and the gate charge of the semiconductor device.

Super junction semiconductor device and associated fabrication method

A JFET having a semiconductor substrate of a first doping type, an epitaxial layer of the first doping type located on the semiconductor substrate, a body region of a second doping type located in the epitaxial layer, a source region of the first doping type located in the epitaxial layer, a gate region of the second doping type located in the body region, and a shielding layer of the second doping type located in the epitaxial layer, wherein the semiconductor substrate is configured as a drain region, the shielding layer is in a conductive path formed between the source region and the drain region.

Junction field effect transistors and associated fabrication methods

This invention discloses a new switching device that includes a drain disposed on a first surface and a source region disposed near a second surface of a semiconductor opposite the first surface. An insulated gate electrode is disposed on top of the second surface for controlling a source to drain current and a source electrode is interposed into the insulated gate electrode for substantially preventing a coupling of an electrical field between the gate electrode and an epitaxial region underneath the insulated gate electrode. The source electrode further covers and extends over the insulated gate for covering an area on the second surface of the semiconductor to contact the source region, An epitaxial layer is disposed above and having a different dopant concentration than the drain region. The gate electrode is insulated from the source electrode by an insulation layer having a thickness depending on a Vgsmax rating of the vertical power device.

A semiconductor device wafer includes a test structure. The test structure includes a layer of material having an angle-shaped test portion disposed on at least a portion of a surface of the semiconductor wafer. A ruler marking on the surface of the semiconductor wafer proximate the test portion is adapted to facilitate measurement of a change in length of the test portion.

Etch depth determination structure

The present technology discloses a semiconductor die integrating a MOSFET device and a Schottky diode. The semiconductor die comprises a MOSFET area comprising the active region of MOSFET, a Schottky diode area comprising the active region of Schottky diode, and a termination area comprising termination structures. Wherein the Schottky diode area is placed between the MOSFET area and the termination area such that the Schottky diode area surrounds the MOSFET area.

Integrated MOSFET devices with Schottky diodes and associated methods of manufacturing

The embodiments of the present disclosure disclose a trench-gate MOSFET device and the method for making the trench-gate MOSFET device. The trench-gate MOSFET device comprises a curving dopant profile formed between the body region and the epitaxial layer so that the portion of the body region under the source metal contact has a smaller vertical thickness than the other portion of the body region. The trench-gate MOSFET device in accordance with the embodiments of the present disclosure has improved UIS capability compared with the traditional trench-gate MOSFET device.

Trench-gate MOSFET device and method for making the same

An integrated circuit includes a junction field effect transistor (JFET) and a power metal oxide semiconductor field effect transistor (MOSFET) on a same substrate. The integrated circuit includes a drain sense terminal for sensing the drain of the power MOSFET through the JFET. The JFET protects a controller or other electrical circuit coupled to the drain sense terminal from high voltage that may be present on the drain of the power MOSFET. The JFET and the power MOSFET share a same drift region, which includes an epitaxial layer formed on the substrate. The integrated circuit may be packaged in a four terminal small outline integrated circuit (SOIC) package. The integrated circuit may be employed in a variety of applications including as an ideal diode.

Integrated field effect transistors with high voltage drain sensing

A semiconductor device and a method for forming the semiconductor device wherein the semiconductor comprises: a trench MOSFET, formed on a semiconductor initial layer, comprising a well region, wherein the semiconductor initial layer has a first conductivity type and wherein the well region has a second conductivity type; an integrated Schottky diode next to the trench MOSFET, comprising a anode metal layer contacted to the semiconductor initial layer; a trench isolation structure, coupled between the trench MOSFET and integrated Schottky diode, configured to resist part of lateral diffusion from the well region; wherein the well region comprises an overgrowth part which laterally diffuses under the trench isolation structure and extends out of it.

Semiconductor device and associated fabrication method

A split trench-gate MOSFET device and method for forming this device is disclosed. The device has a trench gate structure, comprising a shield electrode and two gate electrodes, wherein a substantial portion of shield electrode region is lower than the gate electrode region, and wherein a portion of the shield electrode region extends to the top surface between the two gate electrodes. The device further comprises a source metal layer, contacting to an initial layer, a well region, the shield electrode and a source region at the top surface, wherein the contact between the source metal layer and the initial layer forms a Schottky diode.

Split trench-gate MOSFET with integrated Schottky diode

Fabricating a semiconductor device includes forming a mask on a substrate having a top substrate surface; forming a gate trench in the substrate, through the mask; depositing gate material in the gate trench; removing the mask to leave a gate structure; implanting a body region; implanting a source region; forming a source body contact trench having a trench wall and a trench bottom; forming a plug in the source body contact trench, wherein the plug extends below a bottom of the body region; and disposing conductive material in the source body contact trench, on top of the plug.

Power MOS device fabrication

The present disclosure discloses a lateral DMOS with recessed source contact and method for making the same. The lateral DMOS comprises a recessed source contact which has a portion recessed into a source region to reach a body region of the lateral DMOS. The lateral DMOS according to various embodiments of the present invention may have greatly reduced size and may be cost saving for fabrication.

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San Jose, CA, United States of America

Tiesheng Li