Industrial Technology Research Institute

Electronics Research & Service Organization

Tien-Yu Wu

Yung-Peng Hwung

Ming-Jer Chen

Po-Chin Hsu

Wei-Chen Shen

Ching-Ching Chi

Jyh-Ren Yang

Yunn-Hwa Wang

Yen-Bin Gu

Chu-Chang Lin

An address decoder having non-overlapping word line enable is disclosed having a dynamic logic gate-based decoding section. The decoder includes a deadtime signal generator that produces a pulse at the rising edge of every input clock cycle. The decoder further includes a transmission gate responsive to the deadtime signal for selectively passing the decoder section output signal to a latch. The decoder further includes a NOR logic having an output for coupling to a memory word line which is gated by the deadtime signal to disable the output while the transmission gate passes the decoder output to the latch. When the deadtime pulse transitions to a low state, the latch captures the decoder output signal and enables the output of the NOR gate.

Static random access memory dynamic address decoder with non-overlap

This invention deals with the problem of an error voltage in a MOSFET analog switch sample and hold circuit caused by the turn off charge in the MOSFET analog switch. The invention provides a compensating circuit which can be adjusted to exactly compensate for the turn off charge which causes the error so that the error can be reduced to zero or nearly zero. The compensating circuit can be used in both open loop and closed loop sample and hold circuits. The compensating circuit can be used in combination with a Miller feedback circuit for eliminating the error voltage.

Compensating circuit for MOSFET analog switches

A CMOS current steering switch, especially well-suited for use in high speed switching circuits, has a differential switch transistor pair connected to a node, to which a current source is also connected. The gates of the switch transistor pair are controlled by a pair of buffers. The buffers are designed to avoid both switch transistors being off at the same time by decreasing the switching response time on one transistor of the signal compared to the opposite transistor.

High speed CMOS current switching circuit

A timing control for precharged digital circuits to avoid spurious error appearing at the output due to the slow pull-down of the precharged node after precharging. A NAND gate is used to delay the precharged node siganl transmitting to the output stage until the precharged node is fully discharged. This timing control circuit is used to prevent any spurious peaking of the output of an analog-to-digital converter using precharged bit lines.

Timing control for precharged circuit

Growing community of inventors

Hsinchu, Taiwan

Tien-Yu Wu