Freescale Semiconductor,inc.

Tien Yu T Lee

Jinbang Tang

George R Leal

Victor Adrian Chiriac

Robert Joseph Wenzel

Lakshmi Narayan Ramanathan

Marc Alan Mangrum

Elie A Maalouf

Craig S Amrine

Darrel R Frear

Neil T Tracht

Lizabeth Ann Keser

James R Griffiths

Lizabeth Ann A Keser

An electronic device can include an interconnect level including a bonding pad region. An insulating layer can overlie the interconnect level and include an opening over the bonding pad region. In one embodiment, a conductive stud can lie within the opening and can be substantially encapsulated. In another embodiment, the electronic device can include a barrier layer lying along a side and a bottom of the opening and a conductive stud lying within the opening. The conductive stud can substantially fill the opening. A majority of the conductive stud can lie within the opening. In still another embodiment, a process for forming an electronic device can include forming a conductive stud within the opening wherein from a top view, the conductive stud lies substantially completely within the opening. The process can also include forming a second barrier layer overlying the conductive stud.

Process of forming an electronic device including a conductive stud over a bonding pad region

An integrated circuit assembly includes a panel including an semiconductor device at least partially surrounded by an encapsulant. A panel upper surface and a device active surface are substantially coplanar. The assembly further includes one or more interconnect layers overlying the panel upper surface. Each of the interconnect layers includes an insulating film having contacts formed therein an interconnect metallization formed thereon. A lower surface of the panel is substantially coplanar with either a backside of the device or a lower surface of a thermally and electrically conductive slab that has an upper surface in thermal contact with the device backside. The assembly may also include a set of panel vias. The panel vias are thermally and electrically conductive conduits extending through the panel between the interconnect layer and suitable for bonding with a land grid array (LGA) or other contact structure of an underlying circuit board.

Redistributed chip packaging with thermal contact to device backside

A package assemblyincludes a semiconductor die (e.g., an RF power amplifier)fixed within the cavity of a conductive leadframeusing a thermally and electrically-conductive adhesive material. The semiconductor diehas a first side and a second side, wherein the first side includes at least one active area, and the second side includes at least one contact region. The conductive leadframe (e.g., a copper leadframe)has two planar surfaces and a cavity formed therein. The adhesive materialis configured to couple the semiconductor diewithin the cavity of the conductive leadframesuch that the first side of the semiconductor die is substantially coplanar with the first surface of the conductive leadframe.

Methods and apparatus for a semiconductor device package with improved thermal performance

An electronic device can include an interconnect level () including a bonding pad region (). An insulating layer () can overlie the interconnect level () and include an opening () over the bonding pad region (). In one embodiment, a conductive stud () can lie within the opening () and can be substantially encapsulated. In another embodiment, the electronic device can include a barrier layer () lying along a side and a bottom of the opening () and a conductive stud () lying within the opening (). The conductive stud () can substantially fill the opening (). A majority of the conductive stud () can lie within the opening (). In still another embodiment, a process for forming an electronic device can include forming a conductive stud () within the opening () wherein the conductive stud () lies substantially completely within the opening (). The process can also include forming a second barrier layer () overlying the conductive stud ().

Electronic device including a conductive stud over a bonding pad region

A multi-layer structure () includes a first build-up layer structure () configured to connect to a heat-generating module (), a second build-up layer structure () configured to connect to a substrate, and a middle layer () provided between the first build-up layer structure and the second build-up layer structure, the middle layer including at least one semiconductor component () and a heat spreader (). A first set of thermal vias () extend through the first build-up layer structure to the heat spreader, and a second set of thermal vias (extend through the second build-up layer structure to the heat spreader, wherein at least a portion of the first set of thermal vias is in thermal contact with the heat-generating module.

Methods and apparatus for thermal management in a multi-layer embedded chip structure

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Phoenix, AZ, United States of America

Tien Yu T Lee