National Science Council of Republic of China

Tien Sheng Chao

Chih-hsun Chu

Horng-Chih Lin

The present invention is to develop a proper new process for deep submicron PMOSFET. The characteristic of this process is using Si:Ge:B layer to deposit on the poly-Si film, then go through oxidation or diffusion method to diffuse the boron ion into the poly-Si gate in order to form p-type poly-Si gate. This layer can be etched selectively after spacer etching and reserve a concave gate structure. Thus, it can combine with selective W-CVD to form an excellent p-type poly-Si PMOSFET.

Self-aligned tungsten strapped source/drain and gate technology for deep

A process for suppressing boron penetration in BF.sub.2.sup.+ -implanted P.sup.+ -poly-Si gates provides a nitrided layer between the oxide layer and poly-Si through use of inductively-coupled nitrogen plasma (ICNP) to form an energy barrier which the boron ion can hardly penetrate. The process includes the steps of growing an oxide layer by washing the silicon, introducing nitrogen gas into the inductively-coupled plasma (ICP) system and carrying out nitrogen plasma surface treatment at RF power of 150w to 250w; stacking polysilicon of 3000 .ANG. low pressure chemical vapor deposition (LPCVD) system; implanting BF.sub.2.sup.+ at 5.times.10.sup.15 atom/cm.sup.2 and 50 KeV; removing the surface oxide layer by annealing at 900.degree. C. for a time; and plating Al to form a MOS capacitor and measuring electric properties.

Growing community of inventors

Hsinchu, Taiwan

Tien Sheng Chao