Other

Merck Patent Gmbh

National Yang Ming Chiao Tung University

National Science Council

Merck Patent Gesellschaft

Jmem Technology Co., Ltd

Tien-Sheng Chao

Tan-Fu Lei

Chen-Feng Chang

Ming-Chi Liaw

Shiue-Shin Liu

Tiao-Yuan Huang

Shangjr Gwo

Po-Yi Kuo

Tom Chen

Wen-Tai Lu

Yi-Hsien Lu

Shu-Fen Hu

Ya-Chang Chou

Yung-Chun Wu

An operation method of a multi-bits read only memory includes a step of applying a gate voltage to a conductive gate, a first voltage to a first electrode, and a second voltage to a second electrode. The multi-bits read only memory includes a substrate and a transistor structure with the conductive gate mounted between the first electrode and the second electrode. A multiplicity of M nanowire channels is mounted between the first electrode and the second electrode, and M is a positive integer greater than one. The operation method breaks multiple states of the multi-bits read only memory. The multiple states are programmable and include an istate, and≤ i≤ M. The aforementioned states allow storage of multiple bits on the read only memory, instead of just storing a single bit on the read only memory.

Operation method of multi-bits read only memory

An operation method of a multi-bits read only memory includes a step of applying a gate voltage to a conductive gate, a first voltage to a first electrode, and a second voltage to a second electrode. The multi-bits read only memory of the present invention includes a substrate and a transistor structure with the conductive gate mounted between the first electrode and the second electrode, a first oxide located between the first electrode and the conductive gate, and a second oxide located between the second electrode and the conductive gate. The present invention creates an initial state wherein the transistor structure is not conducting, an intermediate state wherein the first oxide is punched through by the first voltage, and a fully opened state wherein both the first oxide and the second oxide are punched through. The aforementioned states allow storage of multiple bits on the read only memory.

The present invention discloses a manufacturing method of a semiconductor component with a nanowire channel. The method comprises the following steps. The step of forming a stack structure on a substrate is performed. A semiconductor layer is formed on the substrate and the stack structure and further filled into the fillister. The semiconductor layer is patterned to form a source area and a drain area, and the channel region is located between the source area and the drain area. The semiconductor layer located outside the source area, the drain area and the fillister will be removed. And then, the stack structure is then removed. Therefore, the semiconductor layer filled inside the fillister will be exposed to be as a channel. A gate oxide layer is formed to cover the channel, and a gate layer is then formed on the gate oxide layer.

Manufacturing method of a semiconductor component with a nanowire channel

A method for fabricating a single-electron transistor (SET). A one dimensional channel is formed between source and drain on a silicon-on-insulator substrate, and the separated polysilicon sidewall spacer gates are formed by electron-beam lithographically etching process in a self-aligned manner. Operation of the single-electron transistor with self-aligned polysilicon sidewall spacer gates is achieved by applying external bias to the self-aligned polysilicon sidewall spacer gates to form two potential barriers and a quantum dot capable of storage charges between the two potential barriers. A metal upper gate is finally formed and biased to induce a two-dimensional electron gas (2DEG) and control the energy level of the quantum well. Accordingly, the method of the invention comprises a combination of electron beam (E-beam) lithography with multilayer-aligned direct writing technology, oxidation, and wet etching to form a nanoscale one-dimensional channel between source and drain on a silicon-on-insulator substrate.

Single-electron transistor and fabrication method thereof

The present invention relates to a novel process for removing sidewall residue after dry-etching process. Conventionally, after dry-etching, photoresist and sidewall residues are removed by ozone ashing and hot sulfuric acid. Normally, they are hard to be removed completely. It was found in the present invention that the addition of fluorine-containing compound, preferably hydrogen fluoride and ammonium fluoride, in sulfuric acid results in complete removal of photoresist and sidewall residue without the need for stripper. The process is simple and does not affect the original procedures or the other films on the substrate. The present invention also relates to a novel solution for removing sidewall residue after dry-etching, which comprises sulfuric acid and a fluorine-containing compound, preferably hydrogen fluoride and ammonium fluoride, in the range of from 10:1 to 1000:1 by weight.

Solutions and processes for removal of sidewall residue after dry etching

A solution for cleaning silicon semiconductors or silicon oxides comprising H O , NH OH and at least one component A selected from the group consisting of fluoro-containing compounds and other ammonium salts than NH OH, wherein the weight ratio of H O to H O is between 1:5 and 1:50, the weight ratio of NH OH to H O is between 1:5 and 1:50, and the molar ratio of component A to NH OH is between 1:10 and 1:5000 is disclosed. The solution can achieve the efficacy equivalent to that of the conventional RCA two-step cleaning solution within a shorter time by one step and effectively remove contaminants such as organics, dust and metals from the surfaces of silicon semiconductors and silicon oxides without using strong acids such as HCl and H SO .

Solutions for cleaning silicon semiconductors or silicon oxides

The present invention discloses a method of oxidizing a nitride film on a conductive substrate comprising the following steps. First, a conductive substrate is provided, and a nitride film is formed on the main surface of the conductive substrate by performing film deposition process or directly nitridating the surface region of the conductive substrate. Then, a local electrode terminal (such as a conductive probe of a scanning-probe microscope) is provided, and a strong electric field is locally generated between the electrode terminal and the conductive substrate in an oxidizing environment, wherein the strong electric field passes through the nitride film, thereby oxidizing the nitride film region passed by the electric field. The method of oxidizing a nitride film according to the present invention can be applied to define patterns on a nitride film, to record information as memory media, and to form growth templates for the use in chemical selective formation processes.

Method of oxidizing a nitride film on a conductive substrate

A method of forming shallow junctions in a CMOS transistor is disclosed. The method comprises the steps of: (a) forming a diffusion source layer on a N-well region, a P-well region, field oxide layer, and the gates of a CMOS transistor; (b) forming a photoresist layer over the P-well region; (c) carrying out p-type ion implantation to dope a part of the diffusion source layer on the P-well region; (d) removing the photoresist layer on the P-well region; (e) forming a photoresist layer over the N-well region; (f) carrying out n-type ion implantation to dope the other part of the diffusion source layer on the N-well region; (g) removing the photoresist layer on the N-well region; and (h) oxidizing the diffusion source layer and driving the ions therein into the P-well and N-well regions to form shallow junctions, respectively. The present invention has several advantages. First, it is compatible with the conventional CMOS process. Second, it does not require additional mask steps, therefore resulting in a simple process. Third, the CMOS transistors fabricated according to the present invention have shallow junctions, which can alleviate the short channel effect and the defects due to ion implantation.

Growing community of inventors

Hsinchu, Taiwan

Tien-Sheng Chao