Taiwan Semiconductor Manufacturing Comp. Ltd.

Haynes and Boone, Llp

Tien-I Bao

Chung-Ju Lee

Hai-Ching Chen

Shau-Lin Shue

Chen-Hua Douglas Yu

Cheng-Hsiung Tsai

Syun-Ming Jang Jang

Yung-Hsu Wu

Ying-Hao Kuo

Ru-Gun Liu

Chih Wei Lu

Chi-Lin Teng

Hsin-Yen Huang

Bo-Jiun Lin

Yu-Sheng Chang

Hsin-Chieh Yao

Keng-Chu Lin

Tsai-Sheng Gau

Ming-Feng Shieh

Hsiang-Huan Lee

Chun-Hao Tseng

Wan-Yu Lee

Kai-Fang Cheng

Chung-Chi Ko

Chih-Tang Peng

Chien-Hua Huang

Chih-Ming Lai

Shih-Ming Chang

Tai-Chun Huang

Yung-Cheng Lu

Tsung-Min Huang

Jui Hsieh Lai

Shwang-Ming Jeng

Tien-Lu Lin

Tai-I Yang

Ching-Yu Chang

Chin-Hsiang Lin

Chewn-Pu Jou

Chih-Wei Lu

Yen-Chun Huang

Chia-Cheng Chou

Jyu-Horng Shieh

Ken-Hsien Hsieh

Chia-Tien Wu

Kai-Hsuan Lee

Chia-Ying Lee

Lain-Jong Li

Hsin-Hsien Lu

Wei-Ken Lin

Chung-Shi Liu

Sai-Hooi Yeong

Carlos H Diaz

Weng Chang

Bo-Yu Lai

Wen-Kai Lin

Wen-Chih Chiou

Teng-Chun Tsai

Cheng-Chi Chuang

Shy-Jay Lin

Burn Jeng Lin

Chun-Kuang Chen

Yung-Sung Yen

Kuang-Yuan Hsu

Ying-Ho Chen

Hsi-Wen Tien

Jaw-Jung Shin

Po-Cheng Shih

Wei-Chen Chu

Tsu-Hsiu Perng

Ying-Tsung Chen

Hung-Jung Tu

Chia Cheng Chou

Yu-Chieh Liao

Chi-Feng Huang

Yen-Ming Chen

Ying-Lang Wang

Jeng-Horng Chen

Shinn-Sheng Yu

Dian-Hau Chen

Pei-Ren Jeng

Liang-Guang Chen

Hsiang-Ku Shen

Hung-Chang Hsieh

Tsung-Yu Chen

Chung-Long Chang

Tsu Shih

Hui-Min Huang

Chih-Fan Huang

Wan-Yi Kao

Hui-Chi Chen

Chih-Hsien Lin

Cheng-Chung Lin

Szu-An Wu

Hsin-Ping Chen

Chih-Hsiang Yao

Ming-Shih Yeh

Zhen-Cheng Wu

Fang Wen Tsai

Hui-Lin Chang

Chih-Lung Lin

A semiconductor structure and a method for forming the same are provided. The method includes forming a first protruding structure and a second protruding structure over a substrate, and forming a first insulation material layer on the first protruding structure and the second protruding structure. The method includes performing a pre-treatment process on the first insulation material layer to form a first treated insulation material layer, and forming a second insulation material layer on the first treated insulation material layer. The method includes performing a first insulation material conversion process on the first treated insulation material layer and the second insulation material layer. The first protruding structure and the second protruding structure are bent toward opposite directions during the first insulation material conversion process.

Method for forming semiconductor structure with high aspect ratio

The present disclosure involves forming a porous low-k dielectric structure. A plurality of conductive elements is formed over the substrate. The conductive elements are separated from one another by a plurality of openings. A barrier layer is formed over the conductive elements. The barrier layer is formed to cover sidewalls of the openings. A treatment process is performed to the barrier layer. The barrier layer becomes hydrophilic after the treatment process is performed. A dielectric material is formed over the barrier layer after the treatment process has been performed. The dielectric material fills the openings and contains a plurality of porogens.

System and method of forming a porous low-k structure

A circuit device having an interlayer dielectric with pillar-type air gaps and a method of forming the circuit device are disclosed. In an exemplary embodiment, the method comprises receiving a substrate and depositing a first layer over the substrate. A copolymer layer that includes a first constituent polymer and a second constituent polymer is formed over the first layer. The first constituent polymer is selectively removed from the copolymer layer. A first region of the first layer corresponding to the selectively removed first constituent polymer is etched. The etching leaves a second region of the first layer underlying the second constituent polymer unetched. A metallization process is performed on the etched substrate, and the first layer is removed from the second region to form an air gap. The method may further comprise depositing a dielectric material within the etched first region.

Structure and method for a low-k dielectric with pillar-type air-gaps

The present disclosure is generally related to semiconductor devices, and more particularly to a dielectric material formed in semiconductor devices. The present disclosure provides methods for forming a dielectric material layer by a cyclic spin-on coating process. In an embodiment, a method of forming a dielectric material on a substrate includes spin-coating a first portion of a dielectric material on a substrate, curing the first portion of the dielectric material on the substrate, spin-coating a second portion of the dielectric material on the substrate, and thermal annealing the dielectric material to form an annealed dielectric material on the substrate.

Cyclic spin-on coating process for forming dielectric material

An embodiment is a method including recessing a gate electrode over a semiconductor fin on a substrate to form a first recess from a top surface of a dielectric layer, forming a first mask in the first recess over the recessed gate electrode, recessing a first conductive contact over a source/drain region of the semiconductor fin to form a second recess from the top surface of the dielectric layer, and forming a second mask in the second recess over the recessed first conductive contact.

FinFETs and methods of forming FinFETs

A device includes a substrate; a first layer over the substrate, the first layer containing a plurality of fin features and a trench between two adjacent fin features. The device also includes a porous material layer having a first portion and a second portion. The first portion is disposed in the trench. The second portion is disposed on a top surface of the first layer. The first and the second portions contain substantially same percentage of Si, substantially same percentage of O, and substantially same percentage of C.

Porogen bonded gap filling material in semiconductor manufacturing

Some embodiments relate to a semiconductor device disposed on a semiconductor substrate. A dielectric structure is arranged over the semiconductor substrate. First and second metal vias are disposed in the dielectric structure and spaced laterally apart from one another. First and second metal lines are disposed in the dielectric structure and have nearest neighboring sidewalls that are spaced laterally apart from one another by a portion of the dielectric structure. The first and second metal lines contact upper portions of the first and second metal vias, respectively. First and second air gaps are disposed in the portion of the dielectric structure. The first and second air gaps are proximate to nearest neighboring sidewalls of the first and second metal lines, respectively.

Etch damage and ESL free dual damascene metal interconnect

An integrated circuit structure includes a first metal feature formed into a first dielectric layer, a second metal feature formed into a second dielectric layer, the second dielectric layer being disposed on said first dielectric layer, and a via connecting the first metal feature to the second metal feature, wherein a top portion of the via is offset from a bottom portion of the via.

Via connection to a partially filled trench

Embodiments of the present disclosure relate to a FinFET device having gate spacers with reduced capacitance and methods for forming the FinFET device. Particularly, the FinFET device according to the present disclosure includes gate spacers formed by two or more depositions. The gate spacers are formed by depositing first and second materials at different times of processing to reduce parasitic capacitance between gate structures and contacts introduced after epitaxy growth of source/drain regions.

Low-k gate spacer and methods for forming the same

A method includes forming a first layer on a substrate; forming a first plurality of trenches in the first layer by a patterning process; and forming a second plurality of trenches in the first layer by another patterning process, resulting in combined trench patterns in the first layer. A first trench of the second plurality connects two trenches of the first plurality. The method further includes forming dielectric spacer features on sidewalls of the combined trench patterns. A space between two opposing sidewalls of the first trench is completely filled by the dielectric spacer features and another space between two opposing sidewalls of one of the two trenches is partially filled by the dielectric spacer features.

Spacer etching process for integrated circuit design

The present disclosure provides a method for forming an integrated circuit (IC) structure. The method comprises providing a substrate including a conductive feature; forming aluminum (Al)-containing dielectric layer on the conductive feature; forming a low-k dielectric layer on the Al-containing dielectric layer; and etching the low-k dielectric layer to form a contact trench aligned with the conductive feature. A bottom of the contact trench is on a surface of the Al-containing dielectric layer.

Semiconductor structure and method making the same

A semiconductor structure and a method for forming the same are provided. The method includes forming a first protruding structure, a second protruding structure, and a third protruding structure over a substrate. The method also includes performing a depositing process to form a first insulation material layer between the first protruding structure and the second protruding structure. The method further includes performing a first insulation material conversion process onto the first insulation material layer to bend the first protruding structure and the second protruding structure toward opposite directions.

Structure and method for a low-K dielectric with pillar-type air-gaps

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Dayuan, Taiwan

Tien-I Bao