Realtek Semiconductor Inc.

National Yang Ming Chiao Tung University

Tien-Hung Lin

Chia-wei Yu

Jiamei Feng

Hui Huang

Wei Hwang

Po-Hsien Wu

Po-Tsang Huang

Yu-Pin Lin

Ju-Wen Tseng

Jun-Zuo Liu

An image processor circuit includes a first processor circuit and a second processor circuit. In a two-pixel mode, the first processor circuit is configured to process a first part of first input data and the second processor circuit is configured to process a second part of the first input data to generate output data for a display panel to display. In a picture-in-picture mode, the first processor circuit is configured to process second input data to generate main-picture output data and the second processor circuit is configured to process third input data to generate sub-picture output data for the display panel to display.

Image processor circuit supporting two-pixel mode and picture-in-picture mode and image processing method thereof

An image processor circuit includes a first processor circuit and a second processor circuit. In a two-pixel mode, the first processor circuit is configured to process a first part of first input data and the second processor circuit is configured to process a second part of the first input data to generate output data for a display panel to display. The first input data includes K columns, the first part includes 1st to Mth columns of the first input data, and the second part includes Nth to Kth columns of the first input data. N is less than K/and M is greater than K/

Image processor circuit supporting two-pixel mode and image processing method thereof

The present invention provides a chipset for FRC, wherein the chipset includes a first FRC chip and a second FRC chip. The first FRC chip is configured to receive a first part of input image data, and perform a motion compensation on the first part of the input image data to generate a first part of an output image data, wherein a frame rate of the output image data is greater than or equal to a frame rate of the input image data. The second FRC chip is configured to receive a second part of the input image data, and perform the motion compensation on the second part of the input image data to generate a second part of the output image data; wherein the first part and the second part of the output image data are combined into the complete output image data for displaying on a display panel.

Chipset for frame rate control and associated signal processing method

A video processing method for a video processing circuit includes receiving a first video source corresponding to a first pixel rate and a second video source corresponding to a second pixel rate, wherein a processing data rate of a video processing path is greater than or equal to a sum of the first pixel rate and the second pixel rate. The method further includes using the processing data rate to sequentially perform an image processing to a first image of the first video source and a second image of the second video source corresponding to the same display time, to generate a first processed image and a second processed image.

Video processing circuit and method for handling multiple videos using single video processing path capable of increasing processing data rate and saving circuit area

Disclosed are an image tuning device and an image tuning method. The image tuning method includes the following steps: dividing an image area into a plurality of blocks for executing brightness adjustment individually, in which the blocks include a target block and at least one neighboring block; receiving pixel data of the target block to calculate a target block brightness value; receiving pixel data of the at least one neighboring block to calculate at least one neighboring block brightness value; calculating a calculated brightness value of a target pixel within the target block according to the target block brightness value and the at least one neighboring block brightness value; and generating an adjusted brightness value of the target pixel by adjusting an original brightness value of the target pixel according to the calculated brightness value.

Image tuning device and method

On-chip active decoupling capacitors for regulating the voltage of an integrated circuit include a reference voltage generator, a latch-based comparator and switched DECAPs. The latched-based comparator is for comparing a reference voltage generated by the reference voltage generator and a supply voltage of the integrated circuit and outputting a comparison result. The switched DECAPs includes at least two capacitors and a plurality of switches, and coupling the at least two capacitors into a parallel configuration to sink current or a series configuration to source current based on the comparison result output by the latch-based comparator. The aforementioned on-chip active decoupling capacitors not only have lower power consumption, but also larger detection range.

Growing community of inventors

Hsinchu, Taiwan

Tien-Hung Lin