Taiwan Semiconductor Manufacturing Comp. Ltd.

Advanced Micro Devices Corporation

Spansion Llc.

Fasl LLC

Other

Tien-Chun Yang

Ming-Chieh Huang

Chih-Chang Lin

Nian Niles Yang

Chan-Hong Chern

Zhigang Wang

Steven Swei

Yue-Der Chih

Tsung-Ching (Jim) Huang

Yvonne Lin

Pau-Ling Chen

Yonggang Wu

Hyeon-Seag Kim

Ming-Huei Shieh

Shang-Hsuan Liu

Chia-Fu Lee

John JianShi Wang

Amit P Marathe

Yuwen Swei

Shigekazu Yamada

Chiang Pu

Qing Dong

Kurihara Kazuhiro

Kazuhiro Kurihara

Darlene G Hamilton

Binh Quang Le

Tao Wen Chung

Xin Sheng Guo

Edward Franklin Runnion

Ming-Chich Huang

A latch circuit includes first and second supply nodes having a first voltage value and a second voltage below the first voltage value, first and second input nodes, first and second output nodes, a first switch coupled between the first and second output nodes and turned on and off responsive to first and second clock signal states, first and second transistors coupled between the respective second and first output nodes and the second supply node. A second switch is coupled between a first transistor gate and the first input node, a third switch is coupled between a second transistor gate and the second input node, and each is turned on and off responsive to the first and second states. During the first state, one of the first or second transistors is part of a low resistance path from the first power supply node to the second power supply node.

Latch circuit and method of operating the same

A latch circuit includes a power supply node, first and second input nodes, and first and second output nodes. A first switching device is coupled between the first and second output nodes and is turned on and off in response to respective first and second states of a clock signal. A first transistor has a source coupled with a common node, a drain coupled with the second output node, and a gate directly coupled with the first input node, and a second transistor has a source coupled with the common node, a drain coupled with the first output node, and a gate directly coupled with the second input node. A second switching device is coupled between the common node and the power supply node and is turned on and off in response to the respective second and first states of the clock signal.

Latch circuits and method of operating a latch circuit

A memory array includes a plurality of column segments, each column segment including a plurality of columns of memory cells, a plurality of sense amplifiers selectively coupled to each column of the plurality of columns of a corresponding column segment, pluralities of first and second reference cells, and a reference current circuit. The reference current circuit generates a reference current based on a first current generated by a first reference cell programmed to a low logical value and a second current generated by a second reference cell programmed to a high logical value. Each sense amplifier generates a mirror current based on the reference current, and a logical value based on a comparison of the mirror current to a cell current received from a memory cell of a column of the plurality of columns of the corresponding column segment.

Dynamic reference current memory array and method

A sensing circuit includes a current generating circuit and a sensing circuit. The current generating circuit includes a first portion configured to generate a first mirrored current corresponding to a first reference cell programmed to a low logical value, a second portion configured to generate a second mirrored current corresponding to a second reference cell programmed to a high logical value, and a transistor configured to generate a reference voltage by conducting a first reference current equal to a sum of the first mirrored current and the second mirrored current. The sensing circuit includes a sense amplifier configured to generate an output voltage having a logical value based on a second reference current and a cell current of a memory cell, the second reference current being generated from the reference voltage.

Dynamic reference current sensing

A clock generation circuit includes: a two-phase clock generation circuit including first and second branches correspondingly configured to generate a first phase clock signal and a second phase clock signal based correspondingly on a non-inverted clock signal and an inverted clock signal, the first and second branches being cross-coupled with each other; an inverter configured to generate the inverted clock signal based on an input clock signal; and a delay circuit which is non-inverter-based and which is configured to generate the non-inverted clock signal based on the input clock signal, the delay circuit having a predetermined delay.

Clock generation circuit and charge pumping system

A circuit includes a memory cell that generates a cell current having a cell current value, a first reference cell that generates a first current having a first current value, and a second reference cell that generates a second current having a second current value. A current generating circuit generates a reference current having a reference current value based on the first current value and the second current value, and a sense amplifier sums, at a comparison node, a third current having the cell current value and a fourth current having the reference current value. A buffer outputs a voltage on the comparison node as an output of the sense amplifier.

Dynamic reference current sensing using multiple reference cells

A clock generation circuit includes: a two-phase clock generation circuit configured to generate a first phase clock signal and a second phase clock signal based correspondingly on a non-inverted clock signal and an inverted clock signal; an inverter configured to generate the inverted clock signal based on an input clock signal; and a delay circuit which is non-inverter-based and which is configured to generate the non-inverted clock signal based on the input clock signal, the delay circuit having a predetermined delay sufficient to induce symmetry in the first and second phase clock signals such that durational midpoints of overlapping opposite phases of the first and second phase clock signals are substantially aligned.

A delay line circuit including: a coarse-tuning arrangement, including delay units, the coarse-tuning arrangement being configured to coarsely-tune an input signal by transferring the input signal through a selected number of the delay units and thereby producing a first output signal; and a fine-tuning arrangement configured to receive the first output signal at a beginning of a signal path which includes at least three serially-connected inverters, finely-tune the first output signal along the signal path, and produce a second output signal at an end of the signal path; the fine-tuning arrangement including: a speed control unit which is selectively-connectable, and a switching circuit to selectively connect the speed control unit to the signal path based on a process-corner signal.

Delay line circuit and method of operating the same

A clock generation circuit includes: a two-phase clock generation circuit configured to generate a first phase clock signal and a second phase clock signal based correspondingly on a non-inverted clock signal and an inverted clock signal, the first phase clock signal and the second phase clock signal exhibiting non-overlapping logical high states; an inverter configured to generate the inverted clock signal based on an input clock signal; and a delay circuit which is non-inverter-based and which is configured to generate the non-inverted clock signal based on the input clock signal, the delay circuit having a predetermined delay sufficient to cause a difference between a first duration and a second duration within a clock cycle to be less than a predetermined tolerance.

In a charge pump circuit, a first circuit is configured to provide a first node with a first first-voltage level or a first second-voltage level. A second circuit is configured to provide a second node with a second first-voltage level or a second second-voltage level. The first node is coupled with a first end of a first capacitive element. The second node is coupled with a first end of a second capacitive element. A first end of a first voltage transfer circuit is configured to receive an input voltage. A second end of the first voltage transfer circuit is coupled with a second end of the first capacitive element and a first end of a second voltage transfer circuit. A second end of the second voltage transfer circuit is coupled with a second end of the second capacitive element, and is configured to provide an output voltage.

Charge pump circuit and method of operating same

A circuit includes a current generating circuit and a sense amplifier. The current generating circuit includes a first current mirror that generates a first current having a first current value less than a value of a first cell current through a first reference cell, and based on a ratio of the first cell current to the first current. A second current mirror generates a second current having a second current value less than a value of a second cell current through a second reference cell, and based on a ratio of the second cell current to the second current. The current generating circuit generates a reference current having a reference current value based on the first and second current values. The sense amplifier receives a third current having a third current value and generates a voltage output based on the reference and third current values.

A delay line circuit includes: a coarse-tuning arrangement, including delay units; and a fine-tuning arrangement including at least three serially-connected inverters. The coarse-tuning arrangement is configured to receive an input signal and coarsely-tune the input signal, the coarsely-tuning including transferring the input signal through a selected number of the delay units and thereby producing a first output signal. The fine-tuning arrangement is configured to receive the first output signal, finely-tune the first output signal, and produce a second output signal, the finely-tuning including selectively connecting a speed control unit to a node between a corresponding pair of the at least three serially-connected inverters.

Delay line circuit

A latch circuit includes a first input node, a second input node, a first output node, a second output node, a first switching device coupled between the first output node and the second output node, and a first amplification circuit coupled with the first input node, the second input node, the first output node, and the second output node. The first switching device is configured to be turned on in response to a first state of a clock signal and to be turned off in response to a second state of the clock signal. The first amplification circuit is configured to cause a voltage difference across the first switching device based on voltage levels of the first input node and the second input node in response to the first state of the clock signal.

Latch circuit and method of operating the latch circuit

An intellectual property (IP) block portion in an integrated circuit includes a first regulator, a first circuit, a power converter, and a second circuit. The first regulator is configured to receive a supply voltage and to generate a first output voltage. The first circuit is coupled with the first regulator and configured to receive the first output voltage. The power converter includes a charge pump configured to receive the supply voltage and to generate a pumped voltage; and a second regulator configured to receive the supply voltage or the pumped voltage and to generate a second output voltage. The second output voltage has a voltage level greater than a voltage level of the first output voltage. The second circuit is coupled with the power converter and configured to receive the second output voltage.

Regulated power converter and method of operating the same

A clock generation circuit includes a two-phase non-overlapping clock generation circuit, an inverter, and a delay circuit. The two-phase non-overlapping clock generation circuit is configured to generate a first phase clock signal and a second phase clock signal based on a non-inverted clock signal and an inverted clock signal. The first phase clock signal and the second phase clock signal correspond to a same logical value during a first duration and a second duration within a clock cycle. The inverter is configured to generate the inverted clock signal based on an input clock signal. The delay circuit is configured to generate the non-inverted clock signal based on the input clock signal. The delay circuit has a predetermined delay sufficient to cause a difference between the first duration and the second duration to be less than a predetermined tolerance.

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San Jose, CA, United States of America

Tien-Chun Yang