Macronix International Co., Ltd.

Macronix International

Tien-Chu Yang

Kuang-Chao Chen

Chin-Cheng Yang

Chih-Hao Huang

Chao-Lung Lo

Tzong-Hsien Wu

Tahone Yang

ChungTe Hsuan

Chien Hung Chen

A system and method for modifying an integrated circuit (IC) layout includes performing a correction process, such as an optical proximity correction (OPC) process, only on regions within designated blocks that are defined around respective modified structures. An IC layout can be compared to a modified version of the IC layout to detect modified structures. One or more large blocks can then be defined around respective modified structures. A correction process can then be performed on only the one or more large blocks. Small blocks within respective large blocks can then be extracted from the modified IC layout and merged with the original IC layout to generate a final modified and corrected IC layout.

System and method for optical proximity correction of a modified integrated circuit layout

The invention is directed to a method for patterning a material layer. The method comprises steps of providing a material layer. The material layer has a first hard mask layer and a second hard mask layer successively formed thereon. Then, the second hard mask layer is patterned to form a plurality of openings therein. A patterned photoresist layer is formed to cover the second hard mask layer and the patterned photoresist layer exposes a portion of the openings. The first hard mask layer with the patterned photoresist layer and the patterned second hard mask layer together as a mask. Then, the patterned photoresist layer and the patterned second hard mask layer are removed. The material layer is patterned with the patterned first hard mask layer as a mask.

Method for patterning material layer

A method for forming a metal/dielectric multi-layered interconnect. A conductive layer is formed over a substrate. A protective film is formed over the conductive layer. A first high-density plasma fluorinated silica glass (HDP-FSG) layer is formed over the substrate by performing a HDP chemical vapor deposition with a low bias-voltage power. A second HDP-FSG layer is formed over the first HDP-FSG film by performing a HDP chemical vapor deposition at a higher bias-voltage power. A chemical-mechanical polishing is carried out to planarize the FSG layer. A silicon oxynitride is formed over the FSG layer. A via opening is formed in the FSG layer above the conductive layer. A barrier layer is formed onto the via opening and silicon oxynitride. Tungsten is deposited over the substrate filling the via opening. A tungsten chemical-mechanical polishing is carried out to remove excess tungsten and barrier layer above the silicon oxynitride layer.

Method of forming metal/dielectric multi-layered interconnects

A method for forming silicide, at least includes following steps: provide substrate which is covered by semiconductor structure with a rugged topography; form silicon layer on semiconductor structure, where topography of silicon layer is similar to rugged topography; etch silicon layer such that topography of silicon layer is smoothed; form metal layer on silicon layer; and perform thermal process such that suicide layer is made from both metal layer and silicon layer, where suicide layer could be used to form numerous silicide lines. The method could be partially modified as following: provide substrate with rugged first surface; etch substrate such that rugged first surface is changed into smoother second surface; form silicon layer on second surface, where topography of silicon layer is similar to topography of second surface; and form metal layer on silicon layer.

Growing community of inventors

Hsinchu, Taiwan

Tien-Chu Yang