Omnivision Technologies, Inc.

Xilinx, Inc.

Tiemin Zhao

Xinping James He

Datong Chen

Chih-huei Wu

Qingwei Shan

Martin L Voogel

Daniel Gitlin

Sheau-suey Li

Xingping He

An improved active pixel sensor soft reset circuit for reducing image lag while maintaining low reset kTC noise. The circuit pulls down the sensor potential to a sufficiently low level before the soft reset function is completed. The level to which the sensor potential is pulled is set between 0 and the critical potential at which the reset transistor will be on when the soft reset function begins. The timing of the pull down function is such that the sensor is stabilized at the low potential before the soft reset function completes. In one embodiment, the sensor potential is pulled down using a pull-down circuit, which may consist of a CMOS type inverter. In another embodiment, the sensor potential is pulled down by the bit line. Two ways in which the bit line may be pulled down are natural discharge, or by increasing the bias on the loading transistor. Two ways in which the bias on the loading transistor may be increased are a biasing circuit, or by using a pull-down transistor. The active pixel sensor may be implemented with any suitable sensor technology, such as photodiode, photogate, or pinned diode.

APS soft reset circuit for reducing image lag

The active pixel includes a photodiode, a transfer gate, and a reset transistor. The photodiode is substantially covered with an overlying structure, thus protecting the entire surface of the photodiode from damage. This substantially eliminates potential leakage current sources, which result in dark current. In one embodiment, the photodiode is covered by a FOX region in combination with the transfer gate.

Active pixel having reduced dark current in a CMOS image sensor

A method for reducing dark current in a photodiode is disclosed. The photodiode comprises a N-well formed in a P-substrate. The method comprises doping the surface of said N-well with a nitrogen dopant. Alternatively, an oxygen or silicon dopant may be used. Still alternatively, a silicon oxynitride layer may be formed over the N-well.

Surface passivation to reduce dark current in a CMOS image sensor

A photodiode with an optimized floating P&plus; region for a CMOS image sensor. The photodiode is constructed with a P&plus;/Nwell/Psub structure. The Nwell/Psub junction of the photodiode acts as a deep junction photodiode which offers high sensitivity. The P&plus; floating region passivates the silicon surface to reduce dark currents. Unlike a traditional pinned photodiode structure, the P&plus; region in the present invention is not connected to the Pwell or Psub regions, thus making the P&plus; region floating. This avoids the addition of extra capacitance to the cell. The photodiode may be included as part of an active pixel sensor cell, the layout of which is fully compatible with the standard CMOS fabrication process. This type of active pixel sensor cell includes the photodiode, and may be configured with a three transistor configuration for reading out the photodiode signals. Examples of other configurations that the photodiode can be used with include two transistors, four transistors, log scale, as well as its ability to be used in a passive pixel implementation. Also, an additional optional N type layer can be introduced in between the P&plus; region and Nwell to fine tune the junction profile for special applications. In addition, the field oxide region may be made to extend over the photodiode, so as to reduce the exposure of the diode area to the field oxide region edge, which can be a source of dark current due to the high electric fields and mechanical stresses.

Optimized floating P&plus; region photodiode for a CMOS image sensor

An improved pixel structure for a logarithm response image sensor. The pixel structure and read-out sequence provides a method to get a signal free from offsets and gain mismatch due to nonuniformities in the device parameters. An additional transistor is added to a basic logarithmic response pixel structure in order to provide a means for producing a calibration signal level. The calibration transistor is either coupled within the pixel structure itself, or to an extra column line that is coupled to a voltage source. The calibration transistor is therefore not coupled to an extra column line with a calibration current source, and therefore does not have the additional circuitry, power consumption, or control issues associated with a calibration current source type method.

On-chip fixed pattern noise canceling logarithmic response imager sensor

A pass gate circuit includes a pass transistor and a body bias control circuit for biasing the body of the pass transistor to reduce body effect. The body bias control circuit includes one or more control transistors arranged to selectively connect the substrate (body) of the pass transistor to the drain or gate of the pass transistor when predetermined voltages are applied to the drain and gate of the pass transistor. As a result, the pass transistor exhibits a reduced body effect in the on-state. In one embodiment, the body bias control circuit includes a first control transistor having a drain and gate connected to the gate of the pass transistor, a gate connected to the drain of the pass transistor, and a source. The body bias control circuit also includes a second control transistor having a drain connected to the source of the first control transistor, a source connected to a body of the pass transistor, and a gate connected to the drain of the pass transistor. The bodies of the pass transistor, first control transistor and second control transistor are electrically interconnected. With this arrangement, the body of the pass transistor is biased 'high' by the gate of the pass transistor only when both the gate and drain of the pass transistor are at a high voltage level.

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Palo Alto, CA, United States of America

Tiemin Zhao