Omnivision Technologies, Inc.

Tiejun Dai

Rui Wang

Zhe Gao

Zheng Yang

Ling Fu

Hiroaki Ebihara

Liping Deng

Tianjia Sun

Howard E Rhodes

Hsin-Chih Tai

Junzhao Lei

Sohei Manabe

Donghui Wu

Hidetoshi Nozaki

Yu-Shen Yang

Chun-Ming Tang

Duli Mao

Yin Qian

Keiji Mabuchi

Chengming Liu

Eiichi Funatsu

Chao-Fang Tsai

Xiao Xie

Yaowu Mo

Guangbin Zhang

Jian Guo

Min Qu

Cunyu Yang

Richard Mann

Qing Qin

Hiroki Ui

Jingzhou Zhang

Sang Joo Lee

Chen Hui Xu

Dyson Hsinchih Tai

Jizhang Shan

Joseph W Yang

Eric A G Webster

Lindsay Alexander Grant

Shoushun Chen

Yingkan Lin

Dennis Tunglin Lee

Jie Shen

Wei Zheng

Hongli Yang

Jiangtao Kuang

Zhiyong Zhan

Chengcheng Xu

Guannho Tsau

Xiaodong Luo

Wenhao Qiao

Xueqing Wang

Tomas Geurts

Jiayu Guo

Ching Hu

Jing Yin

Cheng-Pin Lin

Le Huang

Shijing Yao

Kuei Chen Liang

Zhengyu Li

Shaomin Ding

Hongtao Yao

Haidong Guo

Chieh-Chien Lin

Zheng Wei

Nozaki Hidetoshi

Pixel designs with reduced LOFIC reset and settling times are disclosed herein. In one embodiment, a pixel cell includes a photosensor configured to photogenerate image charge in response to incident light, a floating diffusion to receive the image charge from the photosensor, a transfer transistor coupled between the floating diffusion and the photosensor to transfer the image charge to the floating diffusion, and a first reset transistor coupled between the floating diffusion and the voltage supply. The pixel cell further includes a capacitor having two ends, and a second reset transistor. A first end of the capacitor is coupled to the floating diffusion. The second reset transistor is coupled between a second end of the capacitor and the voltage supply.

Pixel designs with reduced LOFIC reset and settling times

A pixel circuit includes a photodiode configured to photo generate image charge in response to incident light, a floating diffusion coupled to receive the image charge from the photodiode, a transfer transistor coupled between the photodiode and the floating diffusion to transfer the image charge from the photodiode to the floating diffusion, a reset transistor coupled between a variable voltage source and the floating diffusion, wherein the reset transistor is configured to be switched in response to a reset control signal, and a lateral overflow integration capacitor (LOFIC) coupled between the variable voltage source and the floating diffusion. The variable voltage source is configured to output a high-voltage level during a high conversion gain (HCG) reset signal readout and an HCG image signal readout, and a mid-voltage level during a LOFIC image signal readout and a LOFIC reset signal readout.

CAPMID design in VRFD for HDR structure

A method of counting photons using a plurality of single photon avalanche diodes (SPADs), including initiating a detection phase, enabling each single photon avalanche diode (SPAD) of the plurality of SPADs for a period of time within the detection phase, accumulating a SPAD event from each SPAD of the plurality of SPADs, wherein each SPAD event corresponds to a detection of a single photon, determining a counter code at an end of the detection phase, where the counter code corresponds to accumulated SPAD events, and enabling one or more SPADs of the plurality of SPADs within an exposure phase based on the counter code, where the counter code is greater than an expected number of the SPAD events during the exposure phase, and where the expected number of SPAD events during the exposure phase is based on the counter code that is determined at the end of the detection phase.

Low power single photon avalanche diode photon counter with peak current suppression technique

An imaging system includes a pixel array with odd and even pixel cells. Each of the odd and even pixel cells includes a photodiode, a floating diffusion, a transfer transistor, a reset transistor, a lateral overflow integration capacitor (LOFIC), and an overflow gate (OFG) transistor. The imaging system further includes a readout circuit with a sample and hold (SH) circuit and an analog to digital converter. The OFG transistor of each of the odd and even pixel cells is configured to direct the image charge photogenerated by the respective photodiode away from the respective transfer transistor and reduce photodiode exposure shift during LOFIC readouts during a global transfer period.

Real GS and OFG timing design for 1-by-2 shared HDR VDGS

A pixel circuit includes a first photodiode and a second photodiode. The first and second photodiodes photogenerate charge in response to incident light. A first transfer transistor is coupled to the first photodiode. A first floating diffusion is coupled to the first transfer transistor. A second transfer transistor is coupled to the second photodiode. A second floating diffusion is coupled to the second transfer transistor. A dual floating diffusion transistor is coupled between the first and second floating diffusions. An overflow transistor is coupled to the second photodiode. A capacitor is coupled between a voltage source and the overflow transistor. A capacitor readout transistor is coupled between the capacitor and the second floating diffusion. An anti-blooming transistor coupled between the first photodiode and a power line.

Pixel circuit for high dynamic range image sensor

A global shutter readout circuit includes a pixel enable signal and a first sample and hold (SH) signal that are configured to turn ON a pixel enable transistor and a first storage transistor at a first time during a global transfer period. The pixel enable signal is configured to begin a transition to an OFF level at a second time and complete the transition to the OFF level at a third time to turn OFF the pixel enable transistor. The first SH signal is configured to begin a transition to the OFF level at a fourth time, which occurs after the second and third times, and complete the transition to the OFF level at a fifth time to turn OFF the first storage transistor. An OFF transition duration between the fourth and fifth times is greater than an ON transition duration of the first SH signal at the first time.

Voltage domain global shutter readout circuit timing

A global shutter readout circuit includes a reset transistor coupled between a reset voltage and a bitline. A pixel enable transistor is coupled between the reset transistor and a source follower transistor. First and second terminals of the pixel enable transistor are coupled together in response to a pixel enable signal coupled to a third terminal of the pixel enable transistor. A first storage transistor coupled to the second terminal of the pixel enable transistor and the gate of the source follower transistor. A first storage capacitor is coupled to the first storage transistor. A second storage transistor coupled to the second terminal of the pixel enable transistor and the gate of the source follower transistor. A second storage capacitor is coupled to the second storage transistor. A row select transistor is coupled to the source follower transistor to generate an output signal from the global shutter readout circuit.

Voltage domain global shutter readout circuit

A switch driver circuit includes a plurality of pullup transistors. The plurality of pullup transistors includes a first pullup transistor coupled between a voltage supply and a first output node. A plurality of pulldown transistors includes a first pulldown transistor coupled between the first output node and a ground node. A slope control circuit is coupled to the ground node. A plurality of global connection switches includes a first global connection switch coupled between the first output node and the slope control circuit.

Sample and hold switch driver circuitry with slope control

A pixel array includes pixel cells, each including photodiodes. A source follower is coupled to generate an image signal in response image charge generated by the photodiodes. A first row select transistor is coupled to the source follower to output the image signal of the pixel cell. Pixel cells are organized into columns including a first column and a second column. The first row select transistors of the pixel cells of the first and second columns of pixel cells are coupled to first and second column bitlines, respectively. The pixel cells of the second column of pixel cells further include a second row select transistor coupled to the source follower to output the respective image signal to the first column bitline.

Dual row select pixel for fast pixel binning

A pixel array includes pixel cells disposed in semiconductor material. Each of the pixel cells includes photodiodes, and a floating diffusion to receive image charge from the photodiodes. A source follower is coupled to the floating diffusion to generate an image signal in response image charge from the photodiodes. Drain regions of first and second row select transistors are coupled to a source of the source follower. A common junction is disposed in the semiconductor material between gates of the first and second row select transistors such that the drains of the first and second row select transistors are shared and coupled together through the semiconductor material of the common junction. The pixel cells are organized into a rows and columns with bitlines.

Layout design of dual row select structure

An event driven pixel includes a photodiode configured to photogenerate charge in response to incident light received from an external scene. A photocurrent to voltage converter is coupled to the photodiode to convert photocurrent generated by the photodiode to a voltage. A filter amplifier is coupled to the photocurrent to voltage converter to generate a filtered and amplified signal in response to the voltage received from the photocurrent to voltage converter. A threshold comparison stage is coupled to the filter amplifier to compare the filtered and amplified signal received from the filter amplifier with thresholds to asynchronously detect events in the external scene in response to the incident light. A digital time stamp generator is coupled to asynchronously generate a digital time stamp in response to the events asynchronously detected in the external scene by the threshold comparison stage.

Digital time stamping design for event driven pixel

An event driven sensor includes an arrangement of photodiodes including an inner portion laterally surrounded by an outer portion. An outer pixel cell circuit is coupled to generate an outer pixel value in response to photocurrent generated by the outer portion. The outer pixel value is a binned signal representative of an average value of brightness of incident light on the arrangement of photodiodes. An inner pixel cell circuit is coupled to the inner portion to generate an inner pixel value in response to photocurrent generated by from the inner portion. An event driven circuit is coupled to the outer pixel cell circuit and the inner pixel cell circuit. The event driven circuit is coupled to generate an output signal responsive to an inner brightness indicated by the inner pixel value relative to an outer brightness indicated by the outer pixel value.

Event driven pixel for spatial information extraction

Switching techniques for fast voltage settling in image sensors are described. In one embodiment, an image sensor includes a plurality of lateral overflow integrating capacitor (LOFIC) pixels arranged in rows and columns of a pixel array. The plurality of pixels includes an active pixel configured for exposure to light, and a dummy pixel at least partially protected from exposure to light. A common bitline (BL) is couplable to the active pixel and the dummy pixel. A comparator (OA) is coupled to the bitline. The comparator is configured to receive a pixel voltage (Vx) from the active pixel on one input and a ramp voltage (Vy) on another input. Charge accumulated by the active pixel is determined at least in part by an intersection between the ramp voltage and the pixel voltage.

Auto-zero techniques for lateral overflow integrating capacitor (LOFIC) readout image sensor

Switching techniques for fast voltage settling in image sensors are described. In one embodiment, a transfer gate (TX) driver circuit of an image sensor includes a TX driver configured to provide a TX driver voltage to a plurality of pixels of an image sensor. A power supply (NVDD) is operationally coupled to the TX driver. A first switch (SW) operationally coupling an outside capacitance (Cext) and the TX driver. A second switch (SW) operationally coupling the Cext and the NVDD. A third switch (SW) operationally coupling the NVDD and the TX driver. A falling edge of the TX driver voltage is configured to control a start of data transfer from individual pixels of the plurality of pixels. The SWand the SWare configured in an open position before the falling edge of the TX driver voltage. The SWis configured in a closed position before the falling edge.

Switching techniques for fast voltage settling in image sensors

An image sensor includes a source follower coupled to a photodiode to generate an image signal responsive to photogenerated charge. The image signal is received by image readout circuitry through a row select transistor. A reset transistor resets the photogenerated charge. A first node of mode select circuit is coupled to the reset transistor, a second node is coupled to a pixel supply voltage, and a third node is coupled to an event driven circuit. The mode select circuit couples the first node to the second node during an imaging mode to supply the pixel supply voltage to the reset transistor. The mode select circuit is further configured to couple the first node to the third node during an event driven mode to couple a photocurrent of the photodiode to drive the event driven circuit through the reset transistor to detect changes in the photocurrent.

Hybrid CMOS image sensor with event driven sensing

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Santa Clara, CA, United States of America

Tiejun Dai