Maxim Integrated Products, Inc.

Microsoft Technology Licensing, LLC

Tie Wang

Arkadii V Samoilov

Yi-Sheng Anthony Sun

Zheng Li

Saurabh Nilkanth Athavale

Rey Alvarado

Zhiyong Wang

Bo Long

Yang Yang

Boyi Chen

Xiaofeng Wang

Yanbin Jiang

Matthew R Guevara

Manasi R Deshpande

Yunsong Meng

Yen-Jung Chang

Zhentao Xu

Mark Jerome U Cruz

Embodiments of the disclosed technologies include parsing a query into a first query portion and at least one second query portion, matching an embedding of the at least one second query portion with an embedding that corresponds to a portion of a document of a document set, mapping the portion of the document to a first node of a graph; by a generative artificial intelligence model, constructing a graph query based on at least the first node, executing the graph query on the graph to identify a second node of the graph, extracting a path from the graph, and configuring the path for output at a device.

Generative graph-enhanced information retrieval

The disclosed embodiments provide a system for streamlining machine learning. During operation, the system determines a resource overhead for a baseline version of a machine learning model that uses a set of features to produce entity rankings and a number of features to be removed to lower the resource overhead to a target resource overhead. Next, the system calculates importance scores for the features, wherein each importance score represents an impact of a corresponding feature on the entity rankings. The system then identifies a first subset of the features to be removed as the number of features with lowest importance scores and trains a simplified version of the machine learning model using a second subset of the features that excludes the first subset of the features. Finally, the system executes the simplified version to produce new entity rankings.

Feature removal framework to streamline machine learning

An optical sensor packaging system and method can include: providing a substrate, the substrate including a redistribution pad; mounting an optical sensor to the substrate, the optical sensor including a photo sensitive material formed on a photo sensitive area of an active optical side of the optical sensor; wire-bonding the optical sensor to the substrate with a first bond wire connected from the active optical side to the redistribution pad; and encapsulating the optical sensor, the first bond wire, and the photo sensitive material with an over-mold, the over-mold formed with a top surface co-planar to a surface of the photo sensitive material, the over-mold forming a vertically extended border around the photo sensitive material and around the photo sensitive area, and the over-mold formed above the first bond wire.

Optical sensor packaging system

An optical sensor packaging system and method can include: providing an embedded substrate, the embedded substrate including an embedded chip coupled to a redistribution pad with a redistribution line connecting therebetween; mounting an optical sensor to the embedded substrate, the optical sensor including a photo sensitive material formed on a photo sensitive area of an active optical side of the optical sensor; wire-bonding the optical sensor to the embedded substrate with a first bond wire connected from the active optical side to the redistribution pad; and encapsulating the optical sensor, the first bond wire, and the photo sensitive material with an over-mold, the over-mold formed with a top surface co-planar to a surface of the photo sensitive material, the over-mold forming a vertically extended boarder around the photo sensitive material and around the optical sensing area, and the over-mold formed above the first bond wire.

Wafer-level package devices are described that include multiple die packaged into a single wafer-level package device. In an implementation, a wafer-level package device includes a semiconductor device having at least one electrical interconnection formed therein. At least one semiconductor package device is positioned over the first surface of the semiconductor device. The semiconductor package device includes one or more micro-solder bumps. The wafer-level package device further includes an encapsulation structure disposed over and supported by the semiconductor device for encapsulating the semiconductor package device(s). When the semiconductor package device is positioned over the semiconductor device, each micro-solder bump is connected to a respective electrical interconnection that is formed in the semiconductor device.

Stacked wafer-level package device

A WLP device is provided with a flange shaped UBM or an embedded partial solder ball UBM on top of a copper post style circuit connection.

Enhanced WLP for superior temp cycling, drop test and high current applications

Growing community of inventors

Cupertino, CA, United States of America

Tie Wang