Globalfoundries Inc.

International Business Machines Corporation

Advanced Micro Devices Corporation

Renesas Electronics Corporation

Stmicroelectronics Gmbh

Tibor Bolom

Andrew Herbert Simon

Xunyuan Zhang

Stephan Grunow

Koichi Motoyama

David Lee Rath

Errol Todd Ryan

Chao-Kun Hu

Chengyu Charles Niu

Theodorus E Standaert

Ronald G Filippi

Kaushik Chanda

Robert Seidel

Paul Stephen McLaughlin

Frank Wirbeleit

Thomas Gregory Mckay

Sujatha Sankaran

Frank Koschinsky

Johannes M Van Meer

Bernd Hintze

Frieder Heinrich Baumann

James D Werking

Jihong Choi

Kun Ho Ahn

Frieder Hainrich Baumann

Disclosed are integrated circuit (IC) structure embodiments with a three-dimensional (3D) metal-insulator-metal capacitor (MIMCAP) in back-end-of-the-line (BEOL) metal levels. The MIMCAP includes a plurality of high aspect ratio trenches that extend through at least one relatively thick dielectric layer within the metal levels. Conformal layers of a metal, an insulator and another metal line the trenches and cover the top of the dielectric layer in the area of the MIMCAP. Different configurations for the bottom and top electrode contacts can be used including, for example, one configuration where the top electrode contact is a dual-damascene structure within an ultra-thick metal (UTM) level above the MIMCAP and another configuration where both the top and bottom electrode contacts are such dual-damascene structures. Also disclosed are method embodiments for forming IC structures with such a MIMCAP and these method embodiments can be readily integrated into current BEOL processing, including UTM-level dual-damascene processing.

Three-dimensional (3D) metal-insulator-metal capacitor (MIMCAP) and method

One illustrative method disclosed herein includes, among other things, forming an opening in a layer of insulating material so as to thereby expose at least a portion of a conductive contact, performing a selective deposition process to selectively form a layer of conductive material in the opening and on the conductive contact, performing an anneal process, depositing at least one conductive material above the selectively formed conductive material layer so as to over-fill the opening, and performing at least one planarization process so as to remove excess materials to thereby define a conductive via that is positioned in the opening and conductively coupled to the conductive contact.

Methods of forming an improved via to contact interface by selective formation of a conductive capping layer

One illustrative method disclosed herein includes, among other things, forming an opening in at least one layer of insulating material so as to thereby expose at least a portion of a conductive contact, performing a selective metal silicide formation process to selectively form a metal silicide layer in the opening and on the conductive contact, depositing at least one conductive material above the selectively formed metal silicide layer so as to over-fill the opening, and performing at least one planarization process so as to remove excess materials and thereby define a conductive via that is positioned in the opening and conductively coupled to the selectively formed metal silicide layer and to the conductive contact.

Methods of forming an improved via to contact interface by selective formation of a metal silicide capping layer

Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming a barrier layer overlying a metal line of a metallization layer above a semiconductor substrate using an atomic layer deposition (ALD) process and a physical vapor deposition (PVD) process. A liner-forming material is deposited overlying the barrier layer to form a liner. A conductive metal is deposited overlying the liner.

Methods for fabricating integrated circuits including barrier layers for interconnect structures

A structure having a diffusion barrier positioned adjacent to a sidewall and a bottom of an opening being etched in a layer of dielectric material. The structure also having a metal liner positioned directly on top of the diffusion barrier, a seed layer positioned directly on top of the metal liner, wherein the seed layer is made from a material comprising copper, a copper material positioned directly on top of the seed layer, a metallic cap positioned directly on top of and selective to the copper material, and a capping layer positioned directly on top of and adjacent to the metallic cap.

Copper interconnect with CVD liner and metallic cap

An improved metal interconnect is formed with reduced metal voids and dendrites. An embodiment includes forming a mask layer on a dielectric layer, forming openings in the mask and dielectric layers, depositing a planarization layer over the mask layer and filling the openings, planarizing to remove the mask layer, removing the planarization layer from the openings, and filling the openings with metal. The planarization step prior to depositing the metal removes the etch undercut that occurs during formation of the openings and reduces the aspect ratio in the openings, thereby improving metal fill uniformity.

CMP-first damascene process scheme

A microelectronic structure and a method for fabricating the microelectronic structure use a dielectric layer that is located and formed upon a first conductor layer. An aperture is located through the dielectric layer. The aperture penetrates vertically into the first conductor layer and extends laterally within the first conductor layer beneath the dielectric layer while not reaching the dielectric layer, to form an extended and winged aperture. A contiguous via and interconnect may be formed anchored into the extended and winged aperture while using a plating method, absent voids.

Gap free anchored conductor and dielectric structure and method for fabrication thereof

A test structure for integrated circuit (IC) device fabrication includes a plurality of test structure chains formed at various regions of an IC wafer, each of the plurality of test structure chains including one or more vias; each of the one or more vias in contact with a conductive line disposed thereabove, the conductive line being configured such that at least one dimension thereof varies from chain to chain so as to produce variations in seed layer and liner layer thickness from chain to chain for the same deposition process conditions.

Test structure for determining optimal seed and liner layer thicknesses for dual damascene processing

Methods are provided for semiconductor devices having low contact resistance. The method in accordance with one embodiment of the invention comprises forming an insulating layer overlying a semiconductor substrate, the semiconductor substrate having a device region therein. An opening is formed through the insulating layer to expose a portion of the device region, and the portion of the device region is then electrically contacted by a metallic liner layer. To reduce the resistance of the liner layer and hence the contact, ions of a conductivity determining impurity are implanted into the metallic liner layer. A metal layer is then deposited overlying the metallic liner layer to fill the opening through the insulating layer and to form a conductive plug.

Method for fabricating a semiconductor device

Growing community of inventors

Litomerice, Czechia

Tibor Bolom