Advanced Micro Devices Corporation

Other

Fujitsu Corporation

Spansion Llc.

Cypress Semiconductor Corporation

Tiao-Hua Kuo

Nancy S Leong

Johnny C Chen

Yasushi Kasa

Michael Van Buskirk

Takao Akaogi

Nian Niles Yang

Guowei Wang

Chung K Chang

Sachit Chandra

Michael Allen Van Buskirk

Lee Edward Cleveland

Kazuhiro Kurihara

Darlene G Hamilton

Binh Quang Le

Aaron Lee

Yuan Tang

James Jiahua Yu

Michael A VanBuskirk

Michael David Fliesler

Hounien Chen

Fan W Lai

Johnny Chung-Lee Chen

Takao Akagoi

May Xie

Eric Itakura

Nancy Leong

Johnny Chen

A method is provided for programming a nonvolatile memory array including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region. The method includes receiving a programming window containing a predetermined number of bits that are to be programmed in the array and determining which of the predetermined number of bits are to be programmed in the memory array. The predetermined number of bits are simultaneously programmed to corresponding memory cells in the array. A programming state of the predetermined number of bits in the array is simultaneously verified.

High performance flash memory device capable of high density data storage

A method is provided for programming a nonvolatile memory array including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element having at least two charge storage areas for storing at least two independent charges, a source region and a drain region. The method includes designating at least one memory cell as a high-speed memory cell and pre-conditioning the high-speed memory cells by placing a first of the at least two charge storage areas into a programmed state, and subsequently enabling the programming on the second area with much higher rate.

Multi-bit flash memory device having improved program rate

A simultaneous operation flash memory capable of providing double protection to An OTP sector. The preferred simultaneous operation flash memory comprises an OTP write-protect CAM, which is in a programmed state if the OTP sector is write-protected. In addition, the preferred simultaneous flash memory further includes an OTP sector lock CAM that is electrically connected with the OTP write-protect CAM. The OTP sector lock CAM is used to lock the OTP write-protect CAM in the programmed state, which, in turn, will designate the OTP sector as read only.

OTP sector double protection for a simultaneous operation flash memory

A bank selector encoder comprises a partition indicator circuit having a plurality of partition boundary indicator terminals, a plurality of inverters arranged in a plurality of columns, with each column of the inverters coupled to a respective one of a plurality of columns of ROM cells in a ROM array and a plurality of bank selector code outputs coupled to respective columns of the inverters. The partition boundary indicator terminals are capable of designating a memory partition boundary to identify an upper memory bank and a lower memory bank. The bank selector encoder is capable of generating an identifying bank selector code for each of a plurality of the predetermined memory partition boundaries. The bank selector encoder outputs code bits of a bank selector code based upon the partition boundary indicator terminals.

Bank selector circuit for a simultaneous operation flash memory device with a flexible bank partition architecture

A multiple purpose bus for a flash memory device that allows six sets of data signals to utilize the bus. The multiple purpose bus includes sixteen circuit lines that extend from one end of the memory device to another end of the memory device. Control signals that correspond to each set of data signals couple the sets of data signals to the circuit lines. A grounding circuit is provided that couples the circuit lines to a ground when none of the sets of data signals are utilizing the multiple purpose bus.

Multiple purpose bus for a simultaneous operation flash memory device

An array threshold voltage test mode for a flash memory device is disclosed. During the test mode, a test voltage is routed directly to the gates of the flash memory transistors selected by a given address. If the test voltage causes the selected transistors to change state by crossing their threshold voltage level, the change will be reflected in the data outputs of the device. By varying the test voltages and the addresses and monitoring the data outputs, the array threshold voltage distribution can be determined for the entire device.

Array VT mode implementation for a simultaneous operation flash memory device

A bank selector circuit for a simultaneous operation flash memory device with a flexible bank partition architecture comprises a memory boundary option, a bank selector encoder coupled to receive a memory partition indicator signal from the memory boundary option, and a bank selector decoder coupled to receive a bank selector code from the bank selector encoder. The decoder, upon receiving a memory address, outputs a bank selector output signal to point the memory address to either a lower memory bank or an upper memory bank in the simultaneous operation flash memory device, in dependence upon the selected memory partition boundary.

A variable sector size for a flash memory device is disclosed. The total available memory of the flash memory device is divided into sub-units. Each sub-unit has a pre-decoder coupled with it to enable operations on the memory within that sub-unit. A sector size control register is coupled with pre-decoder enabling logic which is coupled with the pre-decoders. The sector size control register and pre-decoder enabling logic determines how many pre-decoders, and therefore how many sub-units, are activated at a given time for a given memory operation.

Variable sector size for a high density flash memory device

An input circuit for a flash memory device is disclosed. The input circuit includes an input for receiving a voltage signal from an external source representing a digital logic signal. The input circuit further includes a pull up circuit which is coupled with the input and pulls the input to a high logic level when the input is not connected to any external source.

Write protect input implementation for a simultaneous operation flash memory device

A bank selector circuit for a simultaneous operation flash memory device with a flexible bank partition architecture comprises a memory boundary option,, a bank selector encoder,coupled to receive a memory partition indicator signal from the memory boundary option,, and a bank selector decoder,coupled to receive a bank selector code from the bank selector encoder,. The decoder,, upon receiving a memory address, outputs a bank selector output signal to point the memory address to either a lower memory bank or an upper memory bank in the simultaneous operation flash memory device, in dependence upon the selected memory partition boundary.

An acceleration circuit for fast programming and fast chip erase of a non-volatile memory array (,) comprises an acceleration input (,) coupled to a triggering circuit (,) which is capable of generating fast program and fast chip erase commands. In an embodiment, the triggering circuit (,) comprises a high voltage detector (,), which is coupled to the acceleration input (,), and a logic circuit (,), which is coupled to the high voltage detector (,) and has a plurality of command write inputs (,). In a further embodiment, the acceleration voltage is reduced by a regulator (,) to generate a regulated voltage, which is supplied to the memory cells (,) in fast program and fast chip erase modes.

Acceleration circuit for fast programming and fast chip erase of non-volatile memory

The invention is directed to a single power supply pin non-volatile memory device that increases programming speed by providing for two-cycle programming. The invention maintains measures to prevent accidental user overwrites and maintains JEDEC standard compatibility. To provide for two-cycle programming, a three-cycle unlock bypass command is first sent, in one embodiment, after which a plurality of consecutive two-cycle program commands can be sent.

Unlock bypass program mode for non-volatile memory

A method for fast programming of non-volatile memory cells in a non-volatile memory array comprises the steps of providing an acceleration voltage greater than the internal pump voltage supplied by a conventional internal drain pump, providing a program write command, and coupling the acceleration voltage to provide a programming current to all of the bit lines selected to be programmed at a time. In an embodiment, the acceleration voltage is reduced to a drain voltage before it is applied to the drains of the memory cells. In an embodiment in which the flash memory cells comprise typical dual-gate NOR devices, the acceleration voltage is in the range of about 7 V to about 10 V, and the drain voltage is on the order of about 5 V. The sources of the memory cells are grounded during the fast programming operation. In a further embodiment, the method further comprises the steps of detecting the acceleration voltage, generating an acceleration voltage indicator signal in response to the presence of the acceleration voltage, and generating a fast program write command in response to the acceleration voltage indicator signal and the program write command to set the flash memory cells in a fast program mode.

Fast program mode for non-volatile memory

A system for optimizing the equalization pulse of a read sense amplifier is disclosed. A number of capacitor circuits are provided that can be coupled to a timing circuit in a variety of combinations. The different combinations of coupled and decoupled capacitor circuits result in different durational lengths of the equalization pulse. A testing sequence determines the optimal durational length of the equalization pulse by testing the different combinations of coupled capacitors. The optimal combination is then permanently stored in attribute cells for optimizing the equalization pulse in normal operation.

System for optimizing the equalization pulse of a read sense amplifier

A method for fast chip erase of memory cells in a non-volatile memory array comprises the steps of providing an acceleration voltage greater than the internal pump voltage supplied by a conventional internal voltage supply pump, providing an erase write command, and performing a fast erase operation on the memory cells, comprising the step of coupling the acceleration voltage to the sources of the memory cells in a plurality of sectors simultaneously. In an embodiment, a fast preprogramming operation is performed on the memory cells prior to the step of performing the fast erase operation in the fast chip erase mode. In a further embodiment, a fast weak programming (APDE) operation is performed on the memory cells subsequent to the step of performing the fast erase operation in the fast chip erase mode. In an additional embodiment, the step of performing the fast erase operation further comprises the steps of detecting the acceleration voltage, generating an acceleration voltage indicator signal in response to the detection of the acceleration voltage, and generating a fast chip erase write command in response to the acceleration voltage indicator signal and the erase write command.

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San Jose, CA, United States of America

Tiao-Hua Kuo