Boe Technology Group Co., Ltd.

Chengdu Boe Optoelectronics Technology Co., Ltd.

Ordos Yuansheng Optoelectronics Co., Ltd.

Boe Technology Groupco., Ltd.

Beijing Boe Technology Development Co., Ltd.

Tianyi Cheng

Yao Huang

Meng Li

Weiyun Huang

Ming Hu

Yue Long

Haijun Qiu

Cong Liu

Yuanyou Qiu

Binyan Wang

Zhiliang Jiang

Jianpeng Wu

Ziyang Yu

Wenbo Chen

Tiaomei Zhang

Chao Zeng

Mengqi Wang

Feng Wei

Kaipeng Sun

Benlian Wang

Rui Wang

Pinchao Gu

Zhongliu Yang

Erjin Zhao

Qian Xu

Long Ma

Shiqian Dai

Tingliang Liu

Haigang Qing

Lili Du

Shaoru Li

Sen Du

Quanyong Gu

Doyoung Kim

Sifei Ai

Yi Zhang

Fan Yang

Bo Zhang

Qi Liu

Yan Wu

Qiwei Wang

Pan Zhao

Yuqing Yang

Liman Peng

Xingliang Xiao

Yonglin Guo

Lina Wang

Kun Guo

Zhenxiao Tong

Qingqing Yan

Qing He

Xiangnan Pan

Li Wang

Ming Wang

Wen Tan

Yang Yu

Yi Qu

Youngyik Ko

Fei Chen

Yudiao Cheng

Young Yik Ko

Hongjun Zhou

Ni Yang

Wenbin Yang

Chao Wu

Chao Kong

Yuanzheng Guo

Meng Zhao

Chi Yu

Weilin Lai

Jin Fang Yang

Zhong Lu

Liangliang Liu

Zhiyong Yang

Fei Yu

Zihua Li

Baoyun Wu

Zhengkun Li

De Li

Xinxin Jin

Yufei Huo

Jingzhe Fang

Qiyang Wu

Qi Wei

Guowei Zhao

Hongda Cui

Yujing Piao

Shunnv Qian

A scan circuit includes a plurality of stages. A respective stage of the scan circuit includes a second processing subcircuit, which includes a first capacitor, a sixth transistor, and a seventh transistor; and an input subcircuit including a first transistor, and an input signal line configured to provide an input signal to the first transistor. The respective stage of the scan circuit further includes a sixth connecting line connecting a first electrode of the seventh transistor, a second electrode of the sixth transistor, and a second capacitor electrode of the first capacitor together. The sixth connecting line crosses over both the first capacitor electrode and the second capacitor electrode of the first capacitor. A shortest distance between an active layer of the seventh transistor and the input signal line is less than a shortest distance between an active layer of the sixth transistor and the input signal line.

Scan circuit and display apparatus

The present disclosure provides a timing controller applied to a display device, where the display device includes a plurality of pixel circuits, a first driving circuit and a second driving circuit, each of the pixel circuits includes a driving transistor and a writing and compensation circuit; the first driving circuit is configured to sequentially output a first effective level signal to each of first control signal lines, according to a first driving start signal; the second driving circuit is configured to sequentially output a second effective level signal to each of second control signal lines, according to a second driving start signal; and the timing controller is configured to provide the first driving start signal and the second driving start signal during a refresh frame, where the number W of effective pulses in the first driving start signal is more than or equal to 2.

Timing controller, display device, and pixel driving method

A driving circuit includes a first driving signal generation circuit, a first output control circuit, a first gating circuit, a first first energy storage circuit, a first second energy storage circuit and a first output circuit; N is a positive integer; the first gating circuit controls to write the gating input signal into the first first node under the control of the gating control signal; the first output circuit controls to connect the Nth stage of output driving terminal and the first voltage terminal under the control of the potential of the first second node, and controls to connect the Nth stage of output driving terminal and the second voltage terminal under the control of the potential of the first third control node; the first third control node and the first second control node are different nodes.

Driving circuit, driving method, driving module and display device

A pixel driving circuit, including: a driving circuit, connected to a first node, a second node and a third node, and configured to input a driving current to the third node through the second node according to a signal of the first node; a compensation circuit, connected to the first node, the third node and a first gate driving signal end, and configured to turn on the first node and the third node in response to a signal of the first gate driving signal end; a first light-emitting control circuit, connected to the third node, a fourth node and a first enabling signal end, and configured to communicate with the third node and the fourth node in response to a signal of the first enabling signal end; a first reset circuit, connected to the fourth node, a first initial signal end and a first reset signal end, and configured to transmit a signal of the first initial signal end to the fourth node in response to a signal of the first reset signal end; and a second reset circuit, connected to the second node, a second initial signal end and a second reset signal end, and configured to transmit a signal of the second initial signal end to the second node in response to a signal of the second reset signal end.

Pixel driving circuit and driving method therefor, display panel, and display device

A driving circuit includes a driving signal generation circuit, a gating circuit, an output control circuit, an output circuit and a voltage control circuit; the driving signal generation circuit generates an Nth stage of driving signal, the output control circuit connects the first control node and the second node under the control of the potential of the first node; the gating circuit controls to write a gating input signal into the first node under the control of a gating control signal; the voltage control circuit controls a potential of the second node according to a potential of the first node; the output circuit connects the output driving terminal and the first voltage terminal under the control of the potential of the second node, and connects the output driving terminal and the second voltage terminal under the control of the potential of the third control node.

Gate driving circuit having a gating circuit, and driving method thereof

A pixel circuit includes a drive sub-circuit, a first reset sub-circuit, a second reset sub-circuit, and a light emitting element. The drive sub-circuit is configured to generate a drive current between a first electrode and a second electrode of the drive sub-circuit in response to a control signal of a first node. The first reset sub-circuit is configured to write a first reset signal to an anode terminal of the light emitting element in response to a signal of a first light emitting control signal line or a second reset control signal line. The second reset sub-circuit is configured to write a second reset signal to the first electrode or second electrode of the drive sub-circuit in response to a signal of a first reset control signal line. The second reset signal is greater than the first reset signal.

Pixel circuit, driving method therefor, and display apparatus for adjusting a gate-source voltage of a drive transistor using reset signals

A display panel includes a base substrate, a second conductive portion, and first, second and fourth conductive layers located at a side of the base substrate. The first conductive layer includes a first gate line of which orthographic projection extends along a first direction and a partial structure forms a fourth transistor's gate and a first conductive portion forming a driving transistor's gate. The second conductive layer includes a second gate line of which orthographic projection extends along the first direction and is located between orthographic projections of the first conductive portion and the first gate line, and a partial structure forms a second transistor's first gate. Orthographic projection of the second conductive portion at least partially overlaps with that of the first gate line. The fourth conductive layer includes a first connection portion connected to the first and second conductive portions through a via hole.

Display panel, display device

A shift register includes a shift module configured for causing the cascade signal output end to output a cascade signal in response to a signal of the input signal end; an reverse output module configured for causing the reverse signal output end to output a signal reverse to the cascade signal output end in response to a signal of the cascade signal output end; a latch module configured for causing an output end of the latch module to output a control signal of the masking signal end in response to signals of the cascade signal output end and the reverse signal output end of a previous level; and a selection output module configured for providing a signal of the first power supply end or the second power supply end to the driving signal output end in response to a signal of the output end of the latch module.

Shift register, driving method, gate drive circuit and display device

A driving circuit includes a driving signal generation circuit, a gating circuit, an output control circuit and an output circuit; the driving signal generation circuit generates and outputs the Nth stage of driving signal; the gating circuit controls to write the gating input signal into the first node; the output control circuit performs a NAND operation on the Nth stage of driving signal and the potential of the second terminal of the output control circuit to obtain a first output signal; the output circuit inverts the first output signal to obtain and provide an output driving signal through the output driving terminal; N is a positive integer.

A driving circuit, a driving method, a driving module and a display device are provided. The driving circuit includes a driving signal generation circuit, a gating circuit, an output control circuit, an output circuit, a voltage control circuit and a third control node control circuit. The third control node control circuit is electrically connected to the first node and the third control node respectively, and is configured to control the potential of the third control node according to the potential of the first node.

A driving circuit includes a driving signal generation circuit, a gating circuit, an output control circuit, an output circuit, a voltage control circuit and a second node control circuit; the driving signal generation circuit generates an Nth stage of driving signal; the output control circuit controls to connect the first control node and the second node under the control of the potential of the first node; the gating circuit writes a gating input signal into the first node under the control of a gating control signal; the voltage control circuit controls a potential of the second node according to the potential of the first node; the second node control circuit controls to connect the second node and the first voltage terminal under the control of the potential of the first node.

An array substrate is provided. The array substrate includes a plurality of pixel driving circuits. A respective pixel driving circuit of the plurality of pixel driving circuit includes a driving transistor, a compensating transistor, and a first reset transistor. An active layer of the driving transistor is in a first semiconductor material layer. Active layers of the compensating transistor and the first reset transistor are in a second semiconductor material layer different from the first semiconductor material layer. The array substrate includes a third connecting line in a first signal line layer, and connected to a second electrode of the compensating transistor. The third connecting line crosses over at least two control signal lines.

Array substrate and display apparatus

A pixel circuit includes a light-emitting element, a first resetting circuit, a control circuit and a driving circuit. The first resetting circuit writes a first initial voltage into a first node under the control of a first resetting control signal. The control circuit controls a control terminal of the driving circuit to be electrically connected to the first node under the control of a first control signal from the first control terminal, and controls the first node to be electrically connected to the first terminal of the driving circuit under the control of a second control signal from a second control terminal. A first terminal of the driving circuit is electrically connected to the light-emitting element, and the driving circuit is configured to drive the light-emitting element to emit light.

Pixel circuit, method for driving the same and display device

A display substrate and a display device. The display substrate includes a display region, a first connecting wire and a second connecting wire. The display region includes a first display region and a second display region. The first display region includes a plurality of light emitting devices arranged in an array, and the plurality of light emitting devices includes a first light emitting device and a second light emitting device. The second display region includes a plurality of first pixel circuit units, and the plurality of pixel circuit units includes a first pixel circuit and a second pixel circuit. The first connecting wire is connected to the first pixel circuit and the first light emitting device. The second connecting wire is connected to the second pixel circuit and the second light emitting device. The first direction and the second direction intersect each other.

Display substrate and display device

Provided are a display substrate and a display device. The display substrate includes a base substrate, and a driving circuit layer and a light-emitting device layer on the base substrate. The display substrate includes a light-transmitting display area and a normal display area, the normal display area surrounds at least a portion of the light-transmitting display area. The normal display area includes multiple normal driving circuits and multiple dummy driving circuits; some dummy driving circuit are used for driving light-emitting devices located in the light-transmitting display area. The display substrate further includes multiple normal data lines coupled to the normal driving circuits; at least one normal data line is coupled to a data signal input terminal through a data lead; an orthographic projection of the data lead onto the base substrate at least partially overlaps an orthographic projection of the dummy driving circuit onto the base substrate.

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Beijing, China

Tianyi Cheng