Sandisk 3d LLC

Sandisk Technologies Inc.

Sunrise Memory Corporation

Crossbar, Inc.

Aucmos Technologies Usa, Inc.

Tianhong Yan

Luca Giovanni Fasoli

Tz-Yi Liu

Eli Harari

Roy E Scheuerlein

Idan Alrod

Chang Hua Siau

Eran Sharon

George Samachisa

Gopinath Balakrishnan

Ariel Navon

Hagop A Nazarian

Sang Thanh Nguyen

Perumal Ratnam

Christopher John Petti

Scott Brad Herner

Wu-Yi Henry Chien

Jie Zhou

Jeffrey Koon Yee Lee

Robert D Norman

Khandker N Quader

Sayeef Salahuddin

Youn Cheul Kim

Richard S Chernicoff

Yan Li

Sung Hyun Jo

Yingchang Chen

Lin Shih Liu

Yibo Yin

Alexander Bazarsky

Menahem Lasser

Ran Zamir

Yung-Tin Chen

Omer Fainzilber

Dzung Huu Nguyen

Stella Achtenberg

Ishai Ilani

Noam Presman

Cung Vu

John D Nguyen

Tim Chen

A first circuit formed on a first semiconductor substrate is wafer-bonded to a second circuit formed on a second memory circuit, wherein the first circuit includes quasi-volatile or non-volatile memory circuits and wherein the second memory circuit includes fast memory circuits that have lower read latencies than the quasi-volatile or non-volatile memory circuits, as well as logic circuits. The volatile and non-volatile memory circuits may include static random-access memory (SRAM) circuits, dynamic random-access memory (DRAM) circuits, embedded DRAM (eDRAM) circuits, magnetic random-access memory (MRAM) circuits, embedded MRAM (eMRAM), or any suitable combination of these circuits.

High capacity memory circuit with low effective latency

A memory circuit includes: (i) a semiconductor substrate having a planar surface, the semiconductor substrate having formed therein circuitry for memory operations; (ii) a memory array formed above the planar surface, the memory array having one or more electrodes to memory circuits in the memory array, the conductors each extending along a direction substantially parallel to the planar surface; and (iii) one or more transistors each formed above, alongside or below a corresponding one of the electrodes but above the planar surface of the semiconductor substrate, each transistor (a) having first and second drain/source region and a gate region each formed out of a semiconductor material, wherein the first drain/source region, the second drain/source region or the gate region has formed thereon a metal silicide layer; and (b) selectively connecting the corresponding electrode to the circuitry for memory operations.

Vertical thin-film transistor and application as bit-line connector for 3-dimensional memory arrays

A memory structure, includes active columns of polysilicon formed above a semiconductor substrate, each active column includes one or more vertical NOR strings, with each NOR string having thin-film storage transistors sharing a local source line and a local bit line, the local bit line is connected by one segment of a segmented global bit line to a sense amplifier provided in the semiconductor substrate.

Three-dimensional vertical nor flash thin-film transistor strings

Process for forming a vertical thin-film transistor that serves as a connector to a bit-line of a 3-dimensional memory array

A memory circuit includes: (i) a semiconductor substrate having a planar surface, the semiconductor substrate having formed therein circuitry for memory operations; (ii) a memory array formed above the planar surface, the memory array having one or more electrodes to memory circuits in the memory array, the conductors each extending along a direction substantially parallel to the planar surface; and (iii) one or more transistors each formed above, alongside or below a corresponding one of the electrodes but above the planar surface of the semiconductor substrate, each transistor (a) having first and second drain/source region and a gate region each formed out of a semiconductor material, wherein the first drain/source region, the second drain/source region or the gate region has formed thereon a metal silicide layer, and (b) selectively connecting the corresponding electrode to the circuitry for memory operations.

Vertical thing-film transistor and application as bit-line connector for 3-dimensional memory arrays

Three-dimensional vertical NOR flash thin-film transistor strings

A detection circuit that can detect a two-terminal memory cell changing state. For example, in response to electrical stimuli, a memory cell will change state, e.g., to a defined higher resistance state or a defined lower resistance state. Other, techniques do not detect this state change until after the stimuli is completed and a subsequent sensing operation (e.g., read pulse) is performed. The detection circuit can detect the state change during application of the electrical stimuli that cause the state change and can do so by comparing the magnitudes or values of two particular current parameters.

State change detection for two-terminal memory

Two-terminal memory can be formed into a memory array that contains many discrete memory cells in a physical and a logical arrangement. Where each memory cell is isolated from surrounding circuitry by a single transistor, the resulting array is referred to as a 1T1R memory array. In contrast, where a group of memory cells are isolated from surrounding circuitry by a single transistor, the result is a 1TnR memory array. Because memory cells of a group are not isolated among themselves in the 1TnR case, bit disturb effects are theoretically possible when operating on a single memory cell. Read operations are disclosed for two-terminal memory devices configured to mitigate bit disturb effects, despite a lack of isolation transistors among memory cells of an array. Disclosed operations can facilitate reduced bit disturb effects even for high density two-terminal memory cell arrays.

Read operation with data latch and signal termination for 1TNR memory array

A method for programming a memory cell to a predetermined programmed state includesL (a) preparing the memory cell for a write operation; (b) sending a train of programming pulses, each programming pulse being a pulse having a magnitude sufficient to program the memory cell to the predetermined programmed state; (c) preparing the memory cell for a read operation; and (d) reading the programmed state of the memory cell to ascertain whether or not the predetermined programmed state is in the memory cell. In one embodiment, the method repeats steps (a)-(d), when the programmed state of the memory cell is not the predetermined programmed state. In one embodiment, the number of times steps (a)-(d) is repeated is determined based on both a probability of successfully writing the memory cell using a single write pulse and a probability of chaotic switching.

Optimal write method for a ferroelectric memory

State change detection for two-terminal memory utilizing current mirroring circuitry

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San Jose, CA, United States of America

Tianhong Yan