Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd.

Tcl China Star Optoelectronics Technology Co., Ltd.

Shenzhen China Star Optoelectronics Technology Co., Ltd.

Other

Tianhong Wang

Suping Xi

Ping-sheng Kuo

Jing Zhu

Ilgon Kim

Shujhih Chen

Yunxiao Zhong

Yamei Bai

Xiaohui Yao

Yi-fang Chou

Pengpeng Xiong

Ruifa Tan

A storage device includes a signal input terminal, a signal output terminal, a latch, and a controller. The latch is connected between the signal input terminal and the signal output terminal, and the latch is configured to write and store data. The controller is connected between the signal input terminal and the latch. The controller includes a first transistor, a second transistor, and a control switch component, the first transistor and the second transistor are electrically connected to the latch, the control switch component is electrically connected to the first transistor and the second transistor to control the first transistor and the second transistor to be turned on or off. A leakage current of the first transistor is less than a leakage current of the second transistor, and a mobility of the second transistor is greater than a mobility of the first transistor.

Storage device and display

A pixel structure and a display panel are provided. The pixel structure includes a first pixel electrode, a first longitudinal signal line, and a second longitudinal signal line. The first pixel electrode includes a first main pixel area and a first sub-pixel area. The first longitudinal signal line includes a first main line and a first secondary-line. The second longitudinal signal line includes a second main line and a second secondary-line. The first main line and the second main line are arranged in the first main pixel area, and the first secondary-line and the second secondary-line are arranged in the first sub-pixel area.

Liquid crystal display (LCD) panel and pixel structure solving problem of abnormal display due to vertical crosstalk

A light-emitting circuit includes a first transistor, a second transistor, a light-emitting element, a first switching circuit, a second switching circuit, a first capacitor, a current source, and a third switching circuit. The first switching circuit, the second switching circuit, and the third switching circuit are synchronously turned on or synchronously turned off. This not only controls the current flowing through the first switching circuit through the first capacitor, the second switching circuit and the current source to the third power line, and but also controls the current flowing through the third switching circuit, the second transistor through the first capacitor, the second switching circuit and the current source flow to the third power line. Since the current passes through the first transistor and the second transistor, the current flowing through the light-emitting element is reduced, improving adverse effects of parasitic capacitance and wire resistance to the two transistors.

Light-emitting circuit and display panel

A display panel and a manufacturing method thereof are provided. The display panel includes a first substrate, a second substrate, and a liquid crystal layer; a carrier of the first substrate includes a plurality of carriers, a spacer layer of the second substrate includes a plurality of spacers, each carrier disposed corresponds to each spacer, wherein the carrier comprises a base and at least one sub-carrier disposed on the base. The present disclosure adopts different thickness of the carriers to form a step difference, thereby relieving surface pressure of the display panel and saving manufacturing cost.

Display panel and manufacturing method thereof

The present application provides a display panel, comprising a display area and a border area disposed at a periphery of the display area, the border area comprising: an array substrate comprising a first substrate and a gate driver on array (GOA) circuit disposed on the first substrate; a color filter substrate comprising a second substrate and a signal trace disposed on the second substrate; wherein the GOA circuit is overlapped with the signal trace. The present application also relates to a display device.

Display panel and display device

A gate on array (GOA) device and a gate driving circuit are provided. The GOA device includes at least two GOA units. Each of the at least two GOA units includes at least one pull-down maintenance unit. The pull-down maintenance unit at least includes a first thin film transistor. The first thin film transistor includes a base substrate, a first electrode, a second electrode, and a third electrode. An electric potential of the first electrode is different from an electric potential of the second electrode. The first electrode or the second electrode is electrically connected to the third electrode.

GOA device and gate driving circuit

A display panel and a spliced display panel are provided. The display panel includes a GOA circuit, a GOA signal bus, and a chip-on-film area. The present invention changes a traditional way that signal outputs from both sides of the chip-on-film area to a way that signal outputs from each thin-film chip, so as to reduce signal difference in wiring of a GOA bus.

Display panel and spliced display panel

A gate driver on array (GOA) circuit and a display panel are provided. A pull-down maintaining module of the GOA circuit includes an eleventh transistor and a twelfth transistor to remove a residual charge of a second node and a third node to enhance a stability of the GOA circuit.

GOA circuit and display panel

The present application provides a display panel. The display panel includes multiple sub-pixels, multiple data lines, multiple scan lines, and multiple gate fan-out lines. Each two columns of the sub-pixels constitute a sub-pixel group, two data lines are arranged between the two columns of the sub-pixels in the sub-pixel group, and any two adjacent gate fan-out lines are spaced by at least one sub-pixel group. A width of the gate fan-out line is not less than a sum of widths of the two data lines in the sub-pixel group.

Display panel

A display panel is provided. The display panel includes a frame area, and the frame area includes an array substrate and a color filter substrate. The array substrate includes a fanout area configured to dispose a fanout trace. The color filter substrate is disposed opposite to the array substrate. The color filter substrate includes a gate driver on array (GOA) circuit and a signal trace disposed at a side of the GOA circuit. The GOA circuit is electrically connected to the signal trace. The GOA circuit and the signal trace both overlap the fanout area.

A GOA circuit and a display panel are provided. In the GOA circuit, a first clock signal, a second clock signal, and a nth stage clock signal are separated into an input terminal of a first unit and an input terminal of a second unit. This reduces time that a thin film transistor in an inverter is subjected to forward current stress, thereby reducing offset of a threshold voltage of the thin film transistor, improving stability of the thin film transistor, and ensuring a normal output of a scan signal waveform.

GOA circuit and display device

A voltage stabilization circuit, a control method, and a display device are provided. The circuit includes first transistor, second transistor, and third transistor. A source of the first transistor is electrically connected to a drain of the second transistor and a gate of the third transistor, a drain of the first transistor is electrically connected to a first control output terminal of a power management integrated circuit, a gate of the first transistor is electrically connected to a second control output terminal of the power management integrated circuit, a gate of the second transistor is electrically connected to the second control output terminal of the power management integrated circuit, and a drain of the third transistor is electrically connected to a first level terminal for connecting to a display panel. This solves issues of VSSG potential drift caused by transistor aging and further guarantees normal operation of the display panel.

Voltage stabilization circuit, control method, and display device

A control circuit and a display panel applied by the control circuit are provided. The control circuit includes a plurality of stages of shift registers, wherein each of the shift registers includes a first switch, wherein a control terminal of the first switch is configured to receive a first control signal, a first terminal of the first switch is configured to receive the first control signal, and a second terminal of the first switch is electrically coupled to a first node; a second switch, wherein a control terminal of the second switch is electrically coupled to the first node, a first terminal of the second switch is configured to receive a first clock signal, and a second terminal of the second switch is configured to receive a second control signal.

Control circuit and display panel applied by control circuit

A color filter substrate, a display panel and a method of manufacturing color filter substrate are provided. The color filter substrate comprising a first glass substrate and a blocking wall formed on a surface of the first glass substrate which is toward to an array substrate, the blocking wall is a projection structure of the surface of the first glass substrate, and the blocking wall is located in a non-display region. The invention further provides correspondingly display panel and method of manufacturing color filter substrate. The color filter substrate, display panel and method of manufacturing color filter substrate of this disclosure, which using the glass substrate on CF side to be aligning film blocking wall. It could control boundary of the aligning film on CF side, and prevent water vapor pass into inside panel of the aligning film on CF side caused circuit corrosion.

Color filter substrate, display panel and method of manufacturing color filter substrate

The present disclosure discloses a GOA gate driving circuit includes a plurality of GOA driving units arranged in cascade, each level GOA driving unit includes a pull-up control part, a pull-up part, a first pull-down part and a pull-down holding part; wherein, each stage GOA driving unit further includes a second pull-down part coupled between the gate control signal and the reference low level signal, the second pull-down part being controlled by a pull-down signal for lowering the gate control signal to the reference low level signal; the phase of the pull-down signal lags behind the latter two-stage scan driving signal, and the pull-down signal is provided by a separate control chip. The present disclosure further discloses a liquid crystal display including a GOA gate driving circuit as described above.

Growing community of inventors

Guangdong, China

Tianhong Wang