Cambricon Technologies Corporation Limited

Shanghai Cambricon Information Technology Co., Ltd

Cambricon (xi'an) Semiconductor Co., Ltd.

Tian Zhi

Tianshi Chen

Shaoli Liu

Yunji Chen

Jinhua Tao

Qi Guo

Wei Li

Zidong Du

Tao Luo

Zai Wang

Xunyu Chen

Shengyuan Zhou

Yuzhe Luo

Xiaobin Chen

Xiaofu Meng

Zhenxing Zhang

Aspects for backpropagation of a convolutional neural network are described herein. The aspects may include a direct memory access unit configured to receive input data from a storage device and a master computation module configured to select one or more portions of the input data based on a predetermined convolution window. Further, the aspects may include one or more slave computation modules respectively configured to convolute one of the one or more portions of the input data with one of one or more previously calculated first data gradients to generate a kernel gradient, wherein the master computation module is further configured to update a prestored convolution kernel based on the kernel gradient.

Apparatus and methods for training in convolutional neural networks

The present disclosure relates to a method, a device and a computation apparatus for allocating a space address to data in a memory, where the computation apparatus is included in a combined processing apparatus, which includes a general interconnection interface and other processing apparatuses. The computation apparatus interacts with other processing apparatuses to jointly complete computations specified by the user. The combined processing apparatus also includes a storage apparatus. The storage apparatus is respectively connected to the computation apparatus and the other processing apparatuses, and is used for storing data of the computation apparatus and other processing apparatuses. The technical solutions of the present disclosure improve utilization of storage space of the memory.

Method and device for allocating storage addresses for data in memory

The present disclosure provides a counting device and counting method. The device includes a storage unit, a counting unit, and a register unit, where the storage unit may be connected to the counting unit for storing input data to be counted and storing a number of elements satisfying a given condition in the input data after counting; the register unit may be configured to store an address where input data to be counted is stored in the storage unit; and the counting unit may be connected to the register unit, and may be configured to acquire a counting instruction, read a storage address of the input data to be counted in the register unit according to the counting instruction, acquire corresponding input data to be counted in the storage unit, perform statistical counting on a number of elements in the input data to be counted that satisfy the given condition, and obtain a counting result. The counting device and the method may improve the computation efficiency by writing an algorithm of counting a number of elements that satisfy a given condition in input data into an instruction form.

Counting elements in neural network input data

The present disclosure provides a computation device and method. The device may include an input module configured to acquire input data; a model generation module configured to construct an offline model according to an input network structure and weight data; a neural network operation module configured to generate a computation instruction based on the offline model and cache the computation instruction, and compute the data to be processed based on the computation instruction to obtain a computation result; and an output module configured to output a computation result. The device and method may avoid the overhead caused by running an entire software architecture, which is a problem in a traditional method.

Processing apparatus and processing method

The present disclosure provides a neural network processor and neural network computation method that deploy a memory and a cache to perform a neural network computation, where the memory may be configured to store data and instructions of the neural network computation, the cache may be connected to the memory via a memory bus, thereby, the actual compute ability of hardware may be fully utilized, the cost and power consumption overhead may be reduced, parallelism of the network may be fully utilized, and the efficiency of the neural network computation may be improved.

Neural network processor and neural network computation method

A processing device with dynamically configurable operation bit width, characterized by comprising: a memory for storing data, the data comprising data to be operated, intermediate operation result, final operation result, and data to be buffered in a neural network; a data width adjustment circuit for adjusting the width of the data to be operated, the intermediate operation result, the final operation result, and/or the data to be buffered; an operation circuit for operating the data to be operated, including performing operation on data to be operated of different bit widths by using an adder circuit and a multiplier; and a control circuit for controlling the memory, the data width adjustment circuit and the operation circuit. The device of the present disclosure can have the advantages of strong flexibility, high configurability, fast operation speed, low power consumption or the like.

Processing apparatus and processing method with dynamically configurable operation bit width

Aspects for vector operations in neural network are described herein. The aspects may include a vector caching unit configured to store a first vector and a second vector, wherein the first vector includes one or more first elements and the second vector includes one or more second elements. The aspects may further include one or more adders and a combiner. The one or more adders may be configured to respectively add each of the first elements to a corresponding one of the second elements to generate one or more addition results. The combiner may be configured to combine a combiner configured to combine the one or more addition results into an output vector.

Apparatus and methods for vector operations

Aspects for vector operations in neural network are described herein. The aspects may include a vector caching unit configured to store a vector, wherein the vector includes one or more elements. The aspects may further include a computation module that includes one or more comparers configured to compare the one or more elements to generate an output result that satisfies a predetermined condition included in an instruction.

Aspects for vector operations in neural network are described herein. The aspects may include a vector caching unit configured to store a first vector and a second vector, wherein the first vector includes one or more first elements and the second vector includes one or more second elements. The aspects may further include a computation module that includes one or more bitwise processors and a combiner. The bitwise processors may be configured to perform bitwise operations between each of the first elements and a corresponding one of the second elements to generate one or more operation results. The combiner may be configured to combine the one or more operation results into an output vector.

Apparatus and methods for bitwise vector operations

Aspects for generating a dot product for two vectors in neural network are described herein. The aspects may include a controller unit configured to receive a vector load instruction that includes a first address of a first vector and a length of the first vector. The aspects may further include a direct memory access unit configured to retrieve the first vector from a storage device based on the first address of the first vector. Further still, the aspects may include a caching unit configured to store the first vector.

Apparatus and methods for generating dot product

Aspects for vector operations in neural network are described herein. The aspects may include a vector caching unit configured to store a first vector and a second vector. The first vector may include one or more first elements and the second vector may include one or more second elements. The aspects may further include a computation module configured to calculate a cross product between the first vector and the second vector in response to an instruction.

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Beijing, China

Tian Zhi