International Business Machines Corporation

Tian Xia

Peilin Song

Franco Stellari

Stanislav Polonsky

Stephen Dale Wyatt

Alan Weger

John J Ellis-Monaghan

Mark David Jaffe

Keith Aelwyn Jenkins

Richard John Rassel

Tad Jeffrey Wilder

Jack Robert Smith

Pamela Sue Gillis

Anthony J Perri

Mustapha Slamani

Timothy M Platt

Francis Woytowich

Sambasivan Narayan

Jien-Chung Lo

A testing system and method incorporate a test signal generator for generating a test signal with multiple tones uniformly distributed across a wideband having a specific bandwidth. This test signal is generated based on user-specified test signal parameter(s) (e.g., using an orthogonal frequency-division multiplexing (OFDM) spread spectrum technique) and processed (e.g., converted from digital to analog or shifted to a different wideband having the same bandwidth), as necessary, so that it is suitable for application to a specific device under test and so that the tones account for the full range of frequencies with the wideband operation of that device under test. After it is applied to the device under test, the resulting output signal is captured, processed (e.g., converted back to digital or shifted back to the initial wideband), as necessary, and analyzed in order to determine the frequency responses associated with each of the tones.

Circuit test system and method using a wideband multi-tone test signal

The invention disclosed herein provides increased effectiveness of delay and transition fault testing. The method of delay fault testing integrated circuits comprises the steps of creating a plurality of test clock gating groups. The plurality of test clock gating groups comprising elements defining inter-element signal paths within the integrated circuit. Each of the elements of the plurality of test clock gating groups share clock frequency and additional shared characteristics. At least one test signal is commonly and selectively connected through at least one low-speed gate transistor to each of the elements comprising each of the plurality of test clock gating groups based on membership in the test clock gating group. This invention can also be practiced using scan-enable gating groups for the same purposes.

Method and apparatus for increased effectiveness of delay and transition fault testing

A semiconductor die including a semiconductor chip and a test structure, located in a scribe area, is designed and manufactured. The test structure includes an array of complementary metal oxide semiconductor (CMOS) image sensors that are of the same type as CMOS image sensors employed in another array in the semiconductor chip and having a larger array size. Such a test structure is provided in a design phase by providing a design structure in which the orientations of the CMOS image sensors match between the two arrays. The test structure provides effective and accurate monitoring of manufacturing processes through in-line testing before a final test on the semiconductor chip.

Image sensor monitor structure in scribe area

A mechanism for diagnosing broken scan chains based on leakage light emission is provided. An image capture mechanism detects light emission from leakage current in complementary metal oxide semiconductor (CMOS) devices. The diagnosis mechanism identifies devices with unexpected light emission. An unexpected amount of light emission may indicate that a transistor is turned off when it should be turned on or vice versa. All possible inputs may be tested to determine whether a problem exists with transistors in latches or with transistors in clock buffers. Broken points in the scan chain may then be determined based on the locations of unexpected light emission.

Method and apparatus for diagnosing broken scan chain based on leakage light emission

Disclosed are design structures for current sink and source circuits, a charge pump, and a phase locked loop. The current sink and source circuits each have a current mirror that biases a transistor connected to an output node. These circuits each further have a two-stage feedback amplifier to sense the current mirror drain voltage and to control the transistor gate voltage in order to stabilize the current mirror drain voltage independent of output voltage at the output node. The amplifier also increases output resistance at the output node. This configuration allows for a wide operation voltage range and ensures good circuit performance under a very low power supply. A charge pump that incorporates these circuits generates highly matched charging and discharging currents. A PLL that incorporates this charge pump exhibits minimal bandwidth shifts and minimal locking speed and jitter performance degradation.

Structure for a high output resistance, wide swing charge pump

Disclosed are current sink and source circuits, a charge pump that incorporates them, and a phase locked loop that incorporates the charge pump. The current sink and source circuits each have a current mirror that biases a transistor connected to an output node. These circuits each further have a two-stage feedback amplifier to sense the current mirror drain voltage and to control the transistor gate voltage in order to stabilize the current mirror drain voltage independent of output voltage at the output node. The amplifier also increases output resistance at the output node. This configuration allows for a wide operation voltage range and ensures good circuit performance under a very low power supply. A charge pump that incorporates these circuits generates highly matched charging and discharging currents. A PLL that incorporates this charge pump exhibits minimal bandwidth shifts and minimal locking speed and jitter performance degradation.

High output resistance, wide swing charge pump

A programmable jitter signal generator is provided that includes a jitter distribution control unit, a selection unit in signal communication with the jitter distribution control unit, and a delay unit in signal communication with the selection unit; and a corresponding method of generating a programmable jitter signal includes programming a control unit, receiving a reference signal, delaying the received reference signal by a multiple of a base time increment, and selecting a delayed reference signal delayed by a desired multiple of the base time increment in accordance with the programmed control unit.

Growing community of inventors

Essex Junction, VT, United States of America

Tian Xia