International Business Machines Corporation

Globalfoundries Inc.

Tian Shen

Heng Wu

Kevin W Brew

Jingyun Zhang

Ruilong Xie

Kong Boon Yeap

Chih-Chao Yang

Baozhen Li

Yang Liu

Cathryn Jeanne Christiansen

Kai Zhao

Jim Shih-Chun Liang

Ronald Gene Filippi, Jr

Anil Kumar

Yuncheng Song

Patrick Ryan Justison

Seungman Choi

Anjum Mehta

Linjun Cao

A plurality of bit lines corresponding to elements of an input vector intersect a plurality of word lines and a plurality of memristive cells are located at the intersections. At least three cells are grouped together to represent a single matrix element. At least three word lines correspond to each element of an output vector. An A/D converter is coupled to each of the word lines, and for each line, except a first, in each group, a shifter has an input coupled to one of the A/D converters. For each group, an addition-subtraction block adds the output of the A/D converter coupled to the first one of the word lines to outputs of each of the shifters except that for a last one of the word lines, subtracts the output of the last shifter, and outputs a corresponding element of an output vector.

Digital phase change memory (PCM) array for analog computing

A phase change memory, a system, and a method to prevent high resistance drift within a phase change memory through a phase change memory cell with three terminals and self-aligned metal contacts. The phase change memory may include a bottom electrode. The phase change memory may also include a heater proximately connected to the bottom electrode. The phase change memory may also include a phase change material proximately connected to the heater. The phase change memory may also include metal proximately connected to at least two sides of the phase change material. The phase change memory may also include three terminals, where a bottom terminal is located at an area proximately connected to the heater and two top terminals are located at areas proximately connected to the metal.

Three terminal phase change memory with self-aligned contacts

An embodiment of the invention may include a Vertical Field Effect Transistor (VFET) structure, and method of making that structure, having a first VFET and a second VFET. The first VFET may include a single liner between a first source/drain epi and a contact. The second VFET may include two liners between a second source/drain epi and a contact. This may enable proper contact liner matching for differing VFET devices.

VFET contact formation

A method is presented for improved linearity of a phase change memory (PCM) cell structure. The method includes forming a bottom electrode over a substrate, constructing a PCM stack including a plurality of PCM layers each having a different crystallization temperature over the bottom electrode, and forming a top electrode over the PCM stack. The crystallization temperature varies in an ascending order from the bottom electrode to the top electrode.

Phase change memory using multiple stacks of PCM materials

A phase change material switch includes a phase change layer disposed on a metal liner. A gate dielectric layer is disposed on the phase change layer. A metal gate liner is disposed on the gate dielectric layer.

Phase change material switch and method of fabricating same

An eFuse structure including a semiconductor substrate; back end of the line (BEOL) metallization levels on the semiconductor substrate; vias extending through the metallization levels; at least one of the metallization levels including one or more metallic plates in electrical contact with one of the vias, the one or more metallic plates having at least one fusible link in electrical contact with one or more additional vias. The eFuse structure may form a multi-fuse structure such that each fusible link may be fused separately or together at the same time.

EFuse structure with multiple links

One illustrative method disclosed herein includes forming a first transistor for an inverter and forming asymmetrically spaced first and second conductive contact structures that are conductively coupled to the source region and the drain region, respectively, of the transistor. In this example, the first conductive contact structure (for the source region) is positioned a first predetermined target distance from a first side of the gate structure of the transistor, and the second conductive contact structure (for the drain region) is positioned a second predetermined target distance from a second side of the gate structure, wherein the second predetermined target distance is less than the first predetermined target distance.

CMOS inverters with asymmetric contact distances and methods of making such inverters

An exemplary apparatus includes a testing module connected to, and providing a test voltage to, an integrated circuit containing devices under test. The testing module performs a time-dependent dielectric breakdown (TDDB) test on the devices under test. A decoder is connected to the devices under test and the testing module. The decoder selectively connects each device being tested to the testing module. Efuses are connected to a different one of the devices under test. The efuses separately electrically disconnect each of the devices under test from the test voltage upon failure of a corresponding device under test. Protection circuits are connected between the efuses and a ground voltage. Each protection circuit provides a shunt around the decoder upon failure of the device under test.

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Clifton Park, NY, United States of America

Tian Shen