Arm Limited

Tiago Rogerio Muck

Alejandro Rico Carro

Joshua Randall

Bruce James Mathewson

Saurabh Pijuskumar Sinha

Jose Alberto Joao

Douglas James Joseph

An apparatus has decoder circuitry within a first processing element to decode instructions, in order to respond to a sequence of instructions by generating control signals. Processing circuitry within the first processing element is responsive to the control signals to perform operations defined by the sequence of instructions. The decoder circuitry is responsive to a stash hint instruction associated with a given data update instruction in the sequence of instructions, to issue control signals to cause the processing circuitry to respond to the given data update instruction by initiating a modified data update transaction via an interface used to couple the first processing element to interconnect circuitry. The modified data update transaction identifies a given memory address to which updated data is to be written in response to the given data update instruction, and triggers stashing control circuitry accessible via the interconnect circuitry to cause the updated data to be made available for stashing in an associated storage structure of at least one further processing element coupled to the interconnect circuitry.

Technique for controlling stashing of data

Various implementations described herein refer to a device having a multi-layered logic structure with multiple layers including a first layer and a second layer arranged vertically in a stacked configuration. The device may have a first network that links nodes together in the first layer. The device may have a second network that links the nodes in the first layer together by way of the second layer so as to reduce latency related to data transfer between the nodes.

Multi-dimensional routing architecture

A method and apparatus is disclosed for transferring data from a first processor core to a second processor core. The first processor core executes a stash instruction having a first operand associated with a data address of the data. A second processor core is determined to be a stash target for a stash message, based on the data address or a second operand. A stash message is sent to the second processor core, notifying the second processor core of the written data. Responsive to receiving the stash message, the second processor core can opt to store the data in its cache. The data may be included in the stash message or retrieved in response to a read request by the second processing core. The second processor core may be determined by prediction based, at least in part, on monitored data transactions.

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Austin, TX, United States of America

Tiago Rogerio Muck