Freescale Semiconductor,inc.

Nxp Usa, Inc.

Thuy B Dao

Paul W Sanders

Joel E Keys

Jay Paul John

Michael F Petras

Robert A Pryor

Xiaowei Ren

Wayne R Burger

Michael Alan Sadd

Craig T Swift

Chanh M Vuong

Gowrishankar L Chindalore

Olin L Hartin

Dina H Triyoso

Melvy Freeland Miller, Iii

Qiang Li

Hernan A Rueda

Suman K Banerjee

Ross Edward Noble

Philip Li

Low Q associated with passive components of monolithic integrated circuits (ICs) when operated at microwave frequencies can be avoided or mitigated using high resistivity (e.g., &#x2267;100 Ohm-cm) semiconductor substrates and lower resistance inductors for the IC. This eliminates significant in-substrate electromagnetic coupling losses from planar inductors and interconnections overlying the substrate. The active transistor(s) are formed in the substrate proximate the front face. Planar capacitors are also formed over the front face of the substrate. Various terminals of the transistor(s), capacitor(s) and inductor(s) are coupled to a ground plane on the rear face of the substrate using through-substrate-vias to minimize parasitic resistance. Parasitic resistance associated with the planar inductors and heavy current carrying conductors is minimized by placing them on the outer surface of the IC where they can be made substantially thicker and of lower resistance. The result is a monolithic microwave IC previously unobtainable.

Monolithic microwave integrated circuits

Low Q associated with passive components of monolithic integrated circuits (ICs) when operated at microwave frequencies can be avoided or mitigated using high resistivity (e.g., &#x2267;100 Ohm-cm) semiconductor substrates and lower resistance inductors for the IC. This eliminates significant in-substrate electromagnetic coupling losses from planar inductors and interconnections overlying the substrate. The active transistor(s) are formed in the substrate proximate the front face. Planar capacitors are also formed over the front face () of the substrate. Various terminals of the transistor(s), capacitor(s) and inductor(s) are coupled to a ground plane on the rear face of the substrate using through-substrate-vias to minimize parasitic resistance. Parasitic resistance associated with the planar inductors and heavy current carrying conductors is minimized by placing them on the outer surface of the IC where they can be made substantially thicker and of lower resistance. The result is a monolithic microwave IC previously unobtainable.

Methods of making a monolithic microwave integrated circuit

Low Q associated with passive components of monolithic integrated circuits (ICs) when operated at microwave frequencies can be avoided or mitigated using high resistivity (e.g., &#x2267;100 Ohm-cm) semiconductor substrates () and lower resistance inductors (') for the IC (). This eliminates significant in-substrate electromagnetic coupling losses from planar inductors () and interconnections (--&#x2033;) overlying the substrate (). The active transistor(s) (&#x2032;) are formed in the substrate () proximate the front face (). Planar capacitors (&#x2032;) are also formed over the front face () of the substrate (). Various terminals (------&#x2032;, etc.) of the transistor(s) (&#x2032;), capacitor(s) (&#x2032;) and inductor(s) (&#x2032;) are coupled to a ground plane () on the rear face () of the substrate () using through-substrate-vias (&#x2032;) to minimize parasitic resistance. Parasitic resistance associated with the planar inductors (&#x2032;) and heavy current carrying conductors (-&#x2032;) is minimized by placing them on the outer surface of the IC where they can be made substantially thicker and of lower resistance. The result is a monolithic microwave IC () previously unobtainable.

Monolithic microwave integrated circuit

A structure having a substrate includes an opening in the substrate having depth from a top surface of the substrate to a bottom surface of the substrate. A conductive material fills the opening. The opening has a length direction and a width direction and a first and second feature. The first feature and the second feature are spaced apart by a first length. The first feature has first width as a maximum width of the first feature, and the second feature has a second width as the maximum width of the second feature. The opening has a minimum width between the first feature and the second feature that is no more than one fifth the first length. The first width and the second width are each at least twice the minimum width.

Semiconductor structure having a through substrate via (TSV) and method for forming

A method is provided for making a semiconductor device, which comprises (a) providing a semiconductor structure comprising a top gate () and a bottom gate (); (b) creating first (), second and third () openings in the semiconductor structure, wherein the first opening exposes a portion of the bottom gate; (c) filling the first, second and third openings with a conductive material, thereby forming source () and drain () regions in the second and third openings and a conductive region () in the first opening; and (d) forming an electrical contact () to the conductive region.

Double gate MOSFET with coplanar surfaces for contacting source, drain, and bottom gate

A semiconductor device structure includes a substrate having a background doping of a first concentration and of a first conductivity type. A through substrate via (TSV) is through the substrate. A device has a first doped region of a second conductivity on a first side of the substrate. A second doped region is around the TSV. The second doped region has a doping of a second concentration greater than the first concentration and is of the first conductivity type.

A toroidal inductor formed in a semiconductor substrate. Through-silicon vias are used to connect metal layers formed on top and bottom surfaces of the semiconductor substrate. In one embodiment, the vias are elongated and laid out in two concentric circles, an inner circle enclosed by an outer circle. The vias of the outer concentric circle are longer than the vias of the inner circle so that spaces between vias are the same for both circles. In another embodiment, each elongated via may include a plurality of circular vias formed in a line. Metals layers on the top and bottom of the semiconductor substrate are patterned to form wedge shaped connectors between the inner and outer vias to form the spirals of the toroidal inductor. The wedge shaped connectors with elongated vias allow spacing between spirals to be constant.

Method for forming a toroidal inductor in a semiconductor substrate

A method for forming a through substrate via (TSV) comprises forming an opening within a substrate. An adhesion layer of titanium is formed within the via opening, a nucleation layer of titanium nitride is formed over the adhesion layer, and a tungsten layer is deposited over the nucleation layer, the tungsten layer having a thickness less than or equal to a critical film thickness sufficient to provide for film integrity and adhesion stability. A stress relief layer of titanium nitride is formed over the tungsten layer and a subsequent tungsten layer is deposited over the stress relief layer. The subsequent tungsten layer has a thickness less than or equal to the critical film thickness. The method further includes planarizing to expose the interlevel dielectric layer and a top of the TSV and backgrinding a bottom surface of the substrate sufficient to expose a bottom portion of the TSV.

Multilayered through a via

A method of forming a through silicon via includes forming a via opening in a substrate using a hard mask, wherein a polymer is formed in the via opening. A first wet clean removes a first portion of the polymer and forms a first carbon containing oxide along portions of the sidewalls. A first ash process modifies the first carbon containing oxide and removes a second portion of the polymer. A first wet etch removes the modified first carbon containing oxide and a third portion of the polymer. A second ash process forms a second carbon containing oxide along at least a portion of the sidewalls. A second wet etch process removes the second carbon containing oxide and a fourth portions of the polymer. A third ash process forms a third carbon containing oxide along portions of the sidewalls and removes any remaining portions of the polymer.

Method for forming a through silicon via (TSV)

Multilayered through via

A semiconductor fabrication process includes forming a sacrificial layer on a substrate of a donor wafer and implanting hydrogen ions into the substrate through the sacrificial layer to create a stress layer in the substrate. After forming the stress layer, multiple layer stacks are formed on the donor wafer substrate including a bottom gate conductor layer and a bottom gate dielectric layer. An upper surface of the donor wafer is bonded to an upper surface of a handle wafer. An oxide or low-k layer may be formed on the handle wafer. A portion of the substrate of the donor wafer is then cleaved. The bottom gate conductor layer is selected from the group including polysilicon, alpha silicon, alpha germanium, W, Ti, Ta, TiN, and TaSiN.

Method of fabricating a substrate for a planar, double-gated, transistor process

A method is provided for making a semiconductor device, which comprises (a) providing a semiconductor structure comprising a top gate () and a bottom gate (); (b) creating first, second and third openings in the semiconductor structure, wherein the first opening exposes a portion of the bottom gate; (c) filling the first, second and third openings with a conductive material, thereby forming source () and drain () regions in the second and third openings and a conductive region () in the first opening; and (d) forming an electrical contact () to the conductive region.

Method for forming an independent bottom gate connection for buried interconnection including bottom gate of a planar double gate MOSFET

A method of making a semiconductor device includes providing a first wafer and providing a second wafer having a first side and a second side, the second wafer including a semiconductor substrate, a storage layer, and a layer of gate material. The storage layer may be located between the semiconductor structure and the layer of the gate material and the storage layer may be located closer to the first side of the second wafer than the semiconductor structure. The method further includes boding the first side of the second wafer to the first wafer. The method further includes removing a first portion of the semiconductor structure to leave a layer of the semiconductor structure after the bonding. The method further includes forming a transistor having a channel region, wherein at least a portion of the channel region is formed from the layer of the semiconductor structure.

Back-gated semiconductor device with a storage layer and methods for forming thereof

A method for making a semiconductor device comprises providing a first wafer and providing a second wafer having a first side and a second side, the second wafer including a semiconductor structure, a first storage layer, and a layer of gate material, wherein the first storage layer is located between the semiconductor structure and the layer of gate material and closer to the first side of the second wafer than the semiconductor structure. The method further includes bonding the first side of the second wafer to the first wafer and cleaving away a first portion of the semiconductor structure to leave a layer of the semiconductor structure after the bonding. The method further includes forming a second storage layer over the layer of the semiconductor structure and forming a top gate over the second storage layer.

Double-gated non-volatile memory and methods for forming thereof

Double gate transistors () having different bottom gate dielectric thicknesses are formed on a first wafer () by forming a first gate dielectric layer (); removing part of the first gate dielectric layer () from a first area (); forming a second gate dielectric layer () to obtain a thinner bottom gate dielectric layer () over the first area () and a thicker bottom gate dielectric layer () over the second area (); and forming a planar bottom gate layer () over first and second gate dielectric layers. After inverting and bonding the first wafer () to a second wafer (), the bottom gate electrodes (--), bottom gate dielectric layers () and channel regions (--) for the first and second double gate transistors () are selectively etched prior to formation of the top gate structures.

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Austin, TX, United States of America

Thuy B Dao