Cypress Semiconductor Corporation

Thurman John Rodgers

Krishnaswamy Ramkumar

Mira Ben-Tzur

James A Hunter

Bo Soon Chang

Mike Bruner

Warren S Snyder

Harold Kutz

Ali Keshavarzi

Shan Sun

Eric N Mann

Babak A Taheri

Bo Jin

Ritu Shrivastava

Brenor L Brophy

James E Nulty

Peter H Voss

Thomas Davenport

Raymond M Leong

Badrinarayanan Kothandaraman

William Koutny

Daniel J Arnzen

Christopher A Seams

Dan Zupcau

Qi Gu

Arya Bhattacherjee

Klyoko Ikeuchi

Thomas A McCleary

John O Torode

Klyoko Keuchi

Tek Wei

A microelectronic system including hydrogen barriers and copper pillars for wafer level packaging and method of fabricating the same are provided. Generally, the method includes: forming an insulating hydrogen barrier over a surface of a first chip; exposing at least a portion of an electrical contact electrically coupled to a component in the first chip by removing a portion of the insulating hydrogen barrier, the component including a material susceptible to degradation by hydrogen; forming a conducting hydrogen barrier over at least the exposed portion of the electrical contact; and forming a copper pillar over the conducting hydrogen barrier. In one embodiment, the material susceptible to degradation is lead zirconate titanate (PZT) and the microelectronic systems device is a ferroelectric random access memory including a ferroelectric capacitor with a PZT ferroelectric layer. Other embodiments are also disclosed.

Hydrogen barriers in a copper interconnect process

A system includes a controllable voltage generator to generate a power supply voltage. The system also includes a system controller to determine a voltage level associated with the power supply voltage, and prompt the controllable voltage generator to generate the power supply voltage. The system includes a floating gate reference device to generate an absolute voltage reference based, at least in part, on the voltage level associated with the power supply voltage. The system can also include analog circuitry to perform one or more electrical operations responsive to the absolute voltage reference from the floating gate reference device.

Programmable floating gate reference

An improved ESD protection device, integrated circuit and method for programmably altering a sensitivity of the ESD protection device is provided herein. More specifically, an active shunt ESD protection device is provided with an improved trigger circuit design. The improved trigger circuit design enables the sensitivity of the ESD protection device to be altered by providing a variety of programmable elements for adjusting an RC time constant of a slew rate detector contained therein. The programmable elements allow the RC time constant to be altered at the wafer or package level, and avoid the significant time and cost typically associated with conventional trial-and-error adjustment procedures.

Programmable electrostatic discharge (ESD) protection device

A non-planar frame base for an image sensor.

Non-planar packaging of image sensor

A memory device () can include a memory cell block (), a standby current source (), an active current source (), and a clamping device (). In a standby mode, a standby current source () can provide constant standby current Ito memory cell block () via block supply node (). In an active mode, active current source () can provide current to accommodate current necessary for active operations (e.g., accessing the memory cell block). A clamping circuit () can provide additional current in the event a block supply node () potential VCCX collapses due to the presence of micro-defects. In addition, compensation for process variation can be achieved by a self regulating well () to source () back bias that can modulate the threshold voltage of p-channel transistors of memory cells within the well (), reducing overall leakage.

Current source architecture for memory device standby current reduction

In one embodiment, a sacrificial layer is deposited over a base layer. The sacrificial layer is used to define a subsequently formed floating metal structure. The floating metal structure may be anchored into the base layer. Once the floating metal structure is formed, the sacrificial layer surrounding the floating metal structure is etched to create a unity-k dielectric region separating the floating metal structure from the base layer. The unity-k dielectric region also separates the floating metal structure from another floating metal structure. In one embodiment, a noble gas fluoride such as xenon difluoride is used to etch a sacrificial layer of polycrystalline silicon.

Method of forming a floating metal structure in an integrated circuit

A method of performing back-end manufacturing of an integrated circuit (IC) device is disclosed. In one method embodiment, the present invention processes a die-strip through a front-of-line assembly portion which comprises a plurality of sub-stations operating on an in-line basis. The die-strip is then automatically provided to an end-of-line assembly portion. The die-strip is then processed through an end-of-line assembly portion which comprises a plurality of sub-stations operating on an in-line basis. The present embodiment then automatically provides the die-strip to a test assembly portion. The die-strip is then tested by the test portion and then automatically provided to a finish assembly portion. The present embodiment then processes the die-strip through a finish portion which comprises a plurality of sub-stations operating on an in-line basis. Camera systems perform automated visual inspection of dies on the die-strip and maintain a database that can be used for automated reject management.

Method of performing back-end manufacturing of an integrated circuit device

In one embodiment, a metal level includes a plurality of metal lines. A low-k dielectric is deposited over the metal level such that an air gap forms at least between two metal lines. The relatively low dielectric constant of the low-k dielectric reduces capacitance on metal lines regardless of whether an air gap forms or not. The air gap in the low-k dielectric further reduces capacitance on metal lines. The reduced capacitance translates to lower RC delay and faster signal propagation speeds.

Low-k dielectric layer with air gaps

In one embodiment, an environment for testing integrated circuits includes a first die coupled to a tester. The first die includes a removable connection configured to couple a signal from the first die with an adapter layer to a second die being tested. The removable connection may be an elastomeric interposer or a probe, for example.

Probe card with an adapter layer for testing integrated circuits

A method of performing back-end manufacturing of an integrated circuit (IC) device is disclosed. In one method embodiment, the present invention process a die-strip through a front-of-line assembly portion which comprises a plurality of sub-stations operating on an in-line basis. The die-strip is then automatically provided to an end-of-line assembly portion. The die-strip is then processed through an end-of-line assembly portion which comprises a plurality of sub-stations operating on an in-line basis. The present embodiment then automatically provides the die-strip to a test assembly portion. The die-strip is then tested by the test portion and then automatically provided to a finish assembly portion. The present embodiment then processes the die-strip through a finish portion which comprises a plurality of sub-stations operating on an in-line basis. Camera systems perform automated visual inspection of dies on the die-strip and maintain a database that can be used for automated reject management.

An integrated circuit and computer system. According to one embodiment of the present invention an integrated circuit on a single substrate for use with a microprocessor which is coupled to a processor bus is provided, and the integrated circuit includes a cache random access memory array and a data path logic control unit, such as multiplexer which is coupled to the cache random access memory array and has an output for coupling to the processor bus. In one embodiment, a further multiplexer having an output for coupling to a first portion of a memory is provided, and this multiplexer further has input for coupling to a second portion of the memory bus. The IC according the present invention is also for use with a second IC which includes control logic for controlling system memory and for controlling the processor bus and memory bus as well as interfacing to other buses such as peripheral bus. The present invention also provides for improved layout of a cache array with a data path logic management unit as well as power management features for the cache array and a tag RAM with comparator on, in one embodiment, the same chip with the cache array or on an associated chip in another embodiment.

Integrated cache memory with system control logic and adaptation of RAM

A process for minimizing bird's beak in local oxidation of silicon which is compatible with high density (VLSI) semiconductor devices is disclosed. A pad oxide is nitridized using rapid thermal nitridization, which works quickly with minimal thermal cycling of the wafer. A silicon nitride film is then deposited over the nitridized oxide. Both films are exposed to dry plasma etching which gives more consistent results than wet methods. The field oxide is then grown and finally the masking films of the nitridized oxide and silicon nitride are removed, whereby field oxides are grown with minimal bird's beak, and minimal damage to the wafer with a small number of steps. The pad oxide may be grown in the same rapid thermal annealer used for the rapid thermal nitridization. Both cycles (pad oxide growth and nitridization of the pad oxide) can be integrated to 'one' cycle and performed sequentially in the same rapid thermal annealer to increase throughput and improve device quality.

Growing community of inventors

Woodside, CA, United States of America

Thurman John Rodgers